GATE CSE 1990 | Question: 8a

Question

A single bus CPU consists of four general purpose register, namely, $R0, \ldots, R3, \text{ALU}, \text{MAR}, \text{MDR}, \text{PC}, \text{SP}$ and $\text{IR}$ (Instruction Register). Assuming suitable microinstructions, write a microroutine for the instruction, $\text{ADD }R0, R1$.

Answer 1

MAR ←  PC
PC    ←  PC +3
MDR ←  MEM[MAR]
IR     ←  MDR
MAR ← MAR+1
MDR ← MEM[MAR]
R0    ← MDR
MAR ← MAR +1
MDR ← MEM[MAR]
R1    ← MDR
R0    ← R0+R1

Reference: CPU Datapath Diagram from Hamacher

Comments

I am not satisfied with third step of answer, because according to my knowledge, instruction fetched from memory should be stored to IR not to MDR. MDR is used while decoding the instruction, actually MDR will store the operand field of instruction, if present in instruction.

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I am not sure if this is correct. Why are we accessing memory to access Registers Ro and R1?

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this is not how timing signals are generated

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Once you see the Datapath diagram from Hamacher it’ll be clear.

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ADD R0,R1

Here register addressing mode is given right?

Then why are we referencing memory and loading data into R0 and R1?
Register addressing mode means data is present in the R0 and R1

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maybe they are assuming that it is indirect register addressing mode

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why (1) is added to the MAR in the 4^th step and in the 7th   step ?

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@Pranavpurkar ..

Generally it 3byte instruction..

opcode stored in the 1st byte ..

1st Operand register adress stored in the 2nd byte 

2nd Operand rigester address stored in the 3rd byte …

...

 

 

 

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RamaSivaSubrahmanyam

any source to read this?