Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 11

Question

A system has $3$ levels of cache i.e., $L_1, L_2$ and $L_3.$ The access times of $L_1,L_2$ and $L_3$ cache memories are $100$ ns/word, $150$ ns/word and $250$ ns/word, respectively.

$L_1, L_2$ and $L_3$ are divided into blocks of $1,4$ and $8$ words. The hit ratios for $L_1,  L_2$ and $L_3$ are $80\%, 90\%$ and $100\%$, respectively. Assuming memory access has to wait on a cache miss until a complete memory block gets transferred, what is the average access time? 

• A. $103$ ns
• B. $220$ ns
• C. $150$ ns 
• D. $135$ ns 

Comments

why simultaneous is taken , by default it is hieiraichal right ?

Answer 1

On a cache miss a memory block gets transferred from a lower level to higher level one block at a time. And here the block size is always of the higher level.

Since there is no miss on $L_3$ block size of $L_3$ is not relevant for this question.

Average Memory Access time $= 100 + (1-0.8)  \times150 + (1-0.8)(1-0.9) \times 4 \times 250$

$\qquad = 100 + 30 + 20 = 150\;ns$

Comments

i don't think so

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can someone give another method ?

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@Arjun 

Sir please explain, why we multiplied by 4 in the euqation. 

Answer 2

	$L_1$ cache	$L_2$ cache	$Memory$ or $L_3$ cache
$Access\ time\ per\ word$	$100\ ns/w$	$150\ ns/w$	$250\ ns/w$
$Words\ per\ block$	$1 \ W/block$	$4 \ W/block$	$8 \ W/block$
$Hit\ Ratio$	$80 \%$	$90 \%$	$100 \%$

 

So Applying heirarchial access formula we get,

$EMAT = H_{L_1}*T_{L_1} + M_{L_1}* H_{L_2}*(T_{L_1}+T_{L_2}) +M_{L_1}* M_{L_2}*(T_{L_1}+T_{L_2} + T_{memory})$

where,

$H_{L_1} = 0.8$  and $M_{L_1} = 0.2$ 

$H_{L_2} = 0.9$  and $M_{L_2} = 0.1$ 

$T_{L_1} = $ Time to read $1$ Block from $L_1$ cache = $100$ ns

$T_{L_2} = $ Time to access $1$ word(block) from $L_2$ cache and then transfer it to $L_1$ cache = $150$ ns

$T_{memory} = 1000$ ns why ?

see this line

memory access has to wait on a cache miss until a complete memory block gets transferred.

So the complete block of $L_2$ has to be accessed from main memory which consist of $4$ words and each word transfer from main memory to $L_2$ cache takes $250\ ns/word$

So total time to access a block of $4$ words from a main memory  $=4*250 = 1000$ ns

Putting the values in the formula we get,

$EMAT = 0.8*100 + 0.2* 0.9*(100+150) +0.2*0.1*(100+150+ 1000)$

                 $= 80 + 0.2* 0.9*(250) +0.2*0.1*(1250)$

                 $= 80 + 45 +25$

                 $= 150$

So option $c.$ is correct answer.

Comments

here we have to shift whole block not just referred word.

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In the 2017 ques, the read access time is given per word? Is it per word by default or per block?

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In that they have mentioned reffered word first  They have asked hit ratio related to instructions, so i think it should be per word. 1 word = 1 instruction = 1 operand. I am not sure about it.

Answer 3

How cache hierarchies work?

On getting a miss in L1 cache, we won't just go look for it in L2 cache and so on...

We'll transfer that block from L2 to L1, and L3 to L2 if need be.

 

Hence, on a miss in L1, we'll transfer 1 word from L2 to L1.

On a miss in L2, we'll trasfer 4 words from L3 to L1

And L3 can't miss. We can actually treat it as MM here.

The miss penalty would be equal to transferring the required words.

As usual, default will be hierarchical access.

So, $0.8[100]+0.2[0.9(100+150)+0.1(100+150+1000)]$

=> $80+0.2[225+125]$

=> $80+70$

=> $150$