Test by Bikram | Digital Logic | Test 2 | Question: 20

Question

An eight stage ripple counter uses a flip-flop with propagation delay of $75$ nanoseconds. The pulse width of the strobe is $50$ ns. The frequency of the input signal which can be used for proper operation of the counter is approximately:

• A. $1.5$ MHz
• B. $500$ MHz
• C. $2$ MHz
• D. $4$ MHz

Comments

Where can I learn about it? This is the only topic I think, I couldn't find in Mano 5th edition.

---

You may read these :

https://www.quora.com/What-is-the-function-of-a-strobe-function-in-digital-system

http://whatis.techtarget.com/definition/strobe

also see my answer hope you understand it .

---

Helpful Video Solution of similar GATE ECE 1987 Ripple Counter Question: https://youtu.be/S7iUh6vbtis 

Answer 1

8 stages = 2⁸ = 256 states 

8 stage ripple counter means 8 bit standard asynchronous counter by which we mean that :

1. The clock input is supplied to flip flop corresponding to LSB.
2.  The clock input  of  ith flip flop is supplied by the output of (i-1) th flip flop.

Thus if we consider these two points we have to take into account that every flip flop will contribute to the operation of clock.So in other words for proper operation of ripple counter , the clock frequency should be inverse of n*t_pd . 

That means : Clock frequency   =   1 /( n * t_pd )

where n is the number of flip flops and  t_pd is the propagation delay of 1 flip flop.

But in addition to that we know that after applying clock pulse and going through each of the flip flops we have decoder to show output of the counter .But the problem comes when it is transiting to 0 , it may be possible to transit through intermediate states thus producing the decoding error which is commonly known as glitch.

Hence to avoid glitch we apply strobe pulse after the delay introduced by flip flops.

 The clock frequency required to drive the ripple counter  =  1 / (n*t_pd  + T_s) where T_s stands for strobe pulse time.

Now,  substituting n = 8 , t_pd = 75 ns   and T_s  =  50 ns

Hence clock frequency required  =  1 / ((8 * 75 + 50) * 10^-9)  Hz

                                                ~ =  1.538 MHz

Comments

@Bikram Sir, please provide ref to know more about strobe signal and glitch.

---

@ Shubhanshu 

Read :

https://www.quora.com/What-is-the-function-of-a-strobe-function-in-digital-system

http://whatis.techtarget.com/definition/strobe

Answer 2

Maximum time taken for all flip-flops to stabilize is 75ns x 8 + 50 = 650ns. Frequency of operation must be less than 1/650ns = 1.5 MHz.

Comments

Can you please tell how the strobe works here ? I get it that 75ns x 8 will be taken for the O/p to be available at the last stage but how is strobe used here ?

Answer 3

Consider a 3-bit ripple counter. It can count from 0 to 7.

The count will be: 000, 001, 010, 011, 100, 101, 110, 111.

 

In order to go from 3 to 4, all the bits have to be flipped. Since this is ripple (asynchronous) counter — it lacks a global clock and hence all the bits would not change simultaneously.

$Q_0$ will change first, then $Q_1$, then $Q_2$.

This will encounter the worst case delay, and hence for ripple counters to function properly, the clock period to be used must be $\geq$ combined propagation delays of the constituent Flip Flops.

 

Therefore, for an n-bit Ripple Counter

$T_{clk} \geq n*T_p$

 

If we factor in the synchronisation signal (ie strobe signal), then

$T_{clk} \geq n*T_p+T_{strobe}$

---

Now, take the minimum case.

$T_{clk} = 8*75+50=650ns$

If $T=650ns$

=> $F=\frac{1}{650*10^{-9}}Hz$

=> $F = 1.5*10^6Hz$

 

Option A