Stall cycle created due to some miss happen in cache and CPU need to access memory
In this question we can see ,
there are $30$ misses in $L_{1}$ cache for which we need to access $L_{2}.$
In $L_{2}$ there are $20$ hits, but again for $10$ misses we need to access Main Memory.
So, total stall cycles are $20*10+10*(50+10)=800$ stall cycles
Now,
for $250$ memory reference , there are $800$ stall cycles.
for $1$ memory reference , there are $800/250$ stall cycles.
Here, each instruction needs $1.25$ memory reference.
So, for $1.25$ memory reference , there are $(800/250)*1.25=4$ stall cycles or $4 stall/instruction$