Most people have trouble with Cache Misses. You can go through this:
https://gatecse.in/cache-misses/
Thank you very much for clearing that up!
(I'm assuming you intended to say "Even if it is some other policy, we cannot get conflict miss"?)
@Arjun Can you please clarify more on when there will be a capacity miss, the last paragraph says that "We have 256 cache blocks and in the access sequence we accessed only 6 unique memory blocks. A capacity miss is one which is caused due to the shortage in cache size. This is the miss which will happen even if we assume the cache to be fully associative." So we will have a capacity miss when the number of distinct blocks accessed is greater than the number of blocks in the cache memory?
Can you explain more on the last sentence "This is the miss which will happen even if we assume the cache to be fully associative"? What I understand from this is that if the taken example would have been fully associative cache in that case also we will have a capacity miss when the number of distinct block excess > 256. Am I right?
And If the cache in the example would have been fully associative then we would have had 6 compulsory misses and 2 hits in place of conflict miss, Am I correct?
@Arjun sir
can you please check this if my understanding right,
Let Direct Mapped cache #blocks = 4
Mem block address generated by CPU
0 , 4 , 2 , 6 , 2 ,4
all maps to Cache B0
0 ==> compulsory miss
4 ==> compulsory miss
2 ==> compulsory miss
6 ==> compulsory miss
2 ==> conflict miss ( As 2 was in cache earlier but due to conflict got replaced and now referenced again result in miss hence conflict miss)
4 ==> conflict miss same
@Arjun Sir, from the link I deduce that
Direct Map Cache can suffer from Compulsory miss, conflict miss but not from capacity miss.
Fully Associative Cache suffers from Compulsory miss, capacity miss but not from conflict miss.
Set associative cache suffered from Compulsory and Conflict miss but not from capacity miss.
please confirm thus sir.
@shubhanshu
capacity miss, means due to lack of storage, then in any cache mapping mechanism, after the cache full, it should be capacity miss !
But i am doubted on
as per me, this statement is right !
But sir replied to prince07 query as, " if replacement algorithm changes then it may cause conflict miss ! "
i mean to say, if we use FIFO, after all cache blocks full, now any cache block( assume it is not compulsory miss ), then it will conflict with the first one in the FIFO list --- can we say is this miss is conflict miss ?
as per me NO.. due to if there is sufficient cache size this miss not occurred ==> it is capacity miss.
hope sir will clear this doubt :)
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