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Recent questions tagged co-and-architecture
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Unacadmey book
If we have a non pipeline processor which has a cycle time of 40 ns and average CPI of 5.4 .Assuming a 5 stage pipeline model calculate the speed up of pipeline over non pipeline processor.
Praful jha
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CO and Architecture
Jul 8, 2023
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Praful jha
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co-and-architecture
pipelining
speedup
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122
Gate
An I/O device transfers data at a rate of 10MB/s over a 100MB/S bus. The data is transferred in 4KB blocks. If the processor operates at 500MHz, and it takes a total of 5000 cycles to handle each DMA request, find the fraction of CPU time handling the data transfer with and without DMA.
Praful jha
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CO and Architecture
Jul 7, 2023
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Praful jha
558
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co-and-architecture
input-output
dma
0
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Topic: Hit Ratio
The access time of a main memory is 800 ns and cache memory access time is 70 ns. The ratio of read and write requests is 7:3. The hit ratio for read access only is 80%. Calculate the hit ratio for all the memory requests (i.e. both read and write requests) if a write-through policy is used for cache updation.
rahulkarmakar
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in
CO and Architecture
Jun 16, 2023
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rahulkarmakar
395
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co-and-architecture
effective-memory-access
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