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Recent questions tagged multilevel-cache
2
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1
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31
MadeEasy Subject Test: CO & Architecture - Cache Memory
Suppose that in 250 memory references there are 30 misses in first level cache and 10 misses in second level cache. Assume that miss penalty from the L2 cache memory are 50 cycles. The hit time of L2 cache is 10 cycles ... 5 cycles. If there are 1.25 memory references per instruction, then the average stall cycles per instruction is ________.
Pankaj Joshi
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CO and Architecture
Jan 23, 2017
by
Pankaj Joshi
883
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made-easy-test-series
co-and-architecture
multilevel-cache
cache-memory
3
votes
2
answers
32
Cache Access Time
Assume that a system is using write-through cache. It has 70% write hits. The cache operates in look-aside mode with a read-hit ratio of 80%. The program run on the system is such that it has memory reference for read 70% of time and for write is 30%. The main memory ... assume we are using no write allocate policy). Average access time of the system is A. 43 B. 55.2 C. 41.5 D. 60
Samujjal Das
asked
in
CO and Architecture
Jan 22, 2017
by
Samujjal Das
2.7k
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co-and-architecture
multilevel-cache
2
votes
3
answers
33
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 11
A system has $3$ levels of cache i.e., $L_1, L_2$ and $L_3.$ The access times of $L_1,L_2$ and $L_3$ cache memories are $100$ ns/word, $150$ ns/word and $250$ ns/word, respectively. $L_1, L_2$ ... until a complete memory block gets transferred, what is the average access time? $103$ ns $220$ ns $150$ ns $135$ ns
Bikram
asked
in
CO and Architecture
Nov 25, 2016
by
Bikram
9.7k
views
tbb-coa-1
co-and-architecture
cache-memory
multilevel-cache
0
votes
1
answer
34
MadeEasy Test Series: CO & Architecture - Cache Memory
vaishali jhalani
asked
in
CO and Architecture
Nov 24, 2016
by
vaishali jhalani
437
views
made-easy-test-series
co-and-architecture
cache-memory
multilevel-cache
bad-question
2
votes
2
answers
35
Virtually indexed caches
What is virtual indexed cache? How is it different from physical indexed cache? What is virtually indexed physical tagged cache? If possible point me to proper resources.
Veerendra V
asked
in
Operating System
Nov 6, 2016
by
Veerendra V
1.6k
views
cache-memory
multilevel-cache
co-and-architecture
virtual-memory
translation-lookaside-buffer
operating-system
0
votes
0
answers
36
Cache memory access time
If the question is given, L1 cache access time is 150ns/word and one block of L1 cache contains 5words. Should I multiply the access time by 5 or leave it at 150ns as memory is word addressable?
prasitamukherjee
asked
in
CO and Architecture
Aug 6, 2016
by
prasitamukherjee
398
views
co-and-architecture
multilevel-cache
9
votes
3
answers
37
Average access time in cache memory along with hard disk
A system has cache main memory and disk for virtual memory. If referenced word in cache $30$ ns to access it. If it is not in cache $80$ ns to load it in cache and reference is started again. If the word not in memory then $22$ms to ... memory and $80$ ns from memory to cache and start again. Cache hit ratio is $0.8$ memory hit ratio is $0.9$
Pooja Palod
asked
in
CO and Architecture
Jan 31, 2016
by
Pooja Palod
2.2k
views
cache-memory
multilevel-cache
0
votes
2
answers
38
MadeEasy Test Series: CO & Architecture - Cache Memory
Suppose that in $250$ memory references, there are $30$ misses in first level cache and $10$ misses in second level cache. Assume that miss penalty from the L2 cache memory $50$ ... are $1.25$ memory references per instruction, then the average stall cycles per instruction is ________. answer given is $4$
sourav.
asked
in
CO and Architecture
Jan 27, 2016
by
sourav.
541
views
made-easy-test-series
co-and-architecture
cache-memory
multilevel-cache
0
votes
0
answers
39
Gmr in multilevel caches
1.What are global miss rate and local miss rates in two level cache. Lmr is no. of misses on cache / total no. Of access to the cache Gmr is no. of misses on cache / total no. Of cpu generated ref. 2.Global miss rate of both levels of caches will be same or ... . 6 mem. Ref. Are found in l1 and for remaining 4 mem. Ref. L2 is accessed. and only 2 mem. Ref. Are found in l2.
khushtak
asked
in
CO and Architecture
Jan 7, 2016
by
khushtak
433
views
co-and-architecture
multilevel-cache
cache-memory
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