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Previous GATE
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Unanswered Previous GATE Questions
1
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0
answers
31
GATE CSE 1990 | Question: 12a
Consider the following instance of the $0 -1$ Knapsack problem: $\max\; 6X_{1} + 11X_{2} + 16X_{3} + 21X_{4} + 26X_{5}$ Subject to $4X_{1} + 8X_{2} + 12X_{3} + 16X_{4} + 20 X_{5} < 32$ and $X_{i}=0$ ... nodes in the tree in the order in which they are expanded and for each node show the bound on the partial solutions and the decision which leads to that node.
makhdoom ghaya
asked
in
Algorithms
Nov 25, 2016
by
makhdoom ghaya
992
views
gate1990
descriptive
algorithms
branch-and-bound
unsolved
2
votes
0
answers
32
GATE CSE 1990 | Question: 9a
Assume that an instruction test-and-set (TS) has been provided in a machine whose function is as follows: 'the left most bit of the one byte operand is checked and accordingly the condition code (CC) is set to $1$ or $0$. After checking and setting the condition code, implement a critical region using this instruction.
makhdoom ghaya
asked
in
Operating System
Nov 24, 2016
by
makhdoom ghaya
876
views
descriptive
gate1990
operating-system
process-synchronization
critical-section
unsolved
1
vote
0
answers
33
GATE CSE 1990 | Question: 1-ix
The solution to the following linear program $\max$ $X_{1}$ such that $X_{1}+2X_{2} \leq 10$ $X_{1} \leq 8$ $X_{1} \leq 1$ is ____________.
makhdoom ghaya
asked
in
Others
Nov 18, 2016
by
makhdoom ghaya
421
views
gate1990
descriptive
linear-programming
out-of-gate-syllabus
fill-in-the-blanks
1
vote
0
answers
34
GATE CSE 1987 | Question: 5a
Eight $7$-segment LED displays and a keyboard consisting of $28$ keys are to be interfaced to a microprocessor based system. Give the block diagram of the interface circuit using minimum number of port lines from any programmable I/O chip. Use any other IC chip if necessary.
makhdoom ghaya
asked
in
CO and Architecture
Nov 11, 2016
by
makhdoom ghaya
402
views
gate1987
co-and-architecture
input-output
descriptive
out-of-gate-syllabus
1
vote
0
answers
35
GATE CSE 1987 | Question: 3a
Design an $8 \times 8$ multiplier using five $4$-bits adders and $4$ ROM's each programmed to realise $4 \times 4$ multiplier.
makhdoom ghaya
asked
in
Digital Logic
Nov 11, 2016
by
makhdoom ghaya
652
views
gate1987
digital-logic
adder
descriptive
unsolved
1
vote
0
answers
36
GATE CSE 1987 | Question: 1-I
The most satisfactory LED driver circuit using a TTL gate is:
makhdoom ghaya
asked
in
Integrated Circuits
Nov 7, 2016
by
makhdoom ghaya
569
views
gate1987
non-gate
integrated-circuits
out-of-gate-syllabus
0
votes
0
answers
37
GATE CSE 1991 | Question: 07b
It is required to design a hardwired controller to handle the fetch cycle of a single address CPU with a $16$ bit instruction-length. The effective address of an indexed instruction should be derived in the fetch cycle itself. Assume ... bits of an instruction constitute the operand field. Draw the logic schematic of the hardwired controller including the data path.
go_editor
asked
in
CO and Architecture
Apr 24, 2016
by
go_editor
802
views
gate1991
co-and-architecture
control-unit
hardwired-controller
normal
unsolved
descriptive
1
vote
0
answers
38
GATE CSE 1992 | Question: 05,b
Three devices $A, B$ and $C$ are connected to the bus of a computer, input/output transfers for all three devices use interrupt control. Three interrupt request lines INTR$1,$ INTR$2$ and INTR$3$ are available with priority of INTR$1 >$ priority ... priority logic, using an interrupt mask register, in which Priority of $A$ > Priority of $B$ > Priority of $C.$
Arjun
asked
in
CO and Architecture
Dec 19, 2015
by
Arjun
810
views
gate1992
co-and-architecture
interrupts
normal
descriptive
unsolved
5
votes
0
answers
39
GATE CSE 1991 | Question: 6,b
Design a $1024$ bit serial-in/serial-out unidirectional shift register using a $1K\times 1 $bit RAM with a data input $D_{in}$, data output $D_{out}$ and control input $\text{READ}/\overline{\text{WRITE}}$. You may assume the availability of standard SSI and MSI components such as gates, registers and counters.
ibia
asked
in
Digital Logic
Nov 14, 2015
by
ibia
770
views
gate1991
digital-logic
sequential-circuit
shift-registers
out-of-gate-syllabus
5
votes
0
answers
40
GATE CSE 1994 | Question: 23
Suppose we have a computer with single register and only three instructions given below: ... $T \rightarrow (E)\mid id$ Write a syntax directed translation to generate code using this grammar for the computer described above.
Kathleen
asked
in
Compiler Design
Oct 5, 2014
by
Kathleen
1.0k
views
gate1994
compiler-design
grammar
syntax-directed-translation
descriptive
unsolved
3
votes
0
answers
41
GATE CSE 1994 | Question: 16
Every element $a$ of some ring $(R, +, o)$ satisfies the equation $a\;o\;a=a$. Decide whether or not the ring is commutative.
Kathleen
asked
in
Set Theory & Algebra
Oct 5, 2014
by
Kathleen
542
views
gate1994
set-theory&algebra
ring
normal
out-of-gate-syllabus
descriptive
0
votes
0
answers
42
GATE CSE 1994 | Question: 1.3
Backward Euler method for solving the differential equation $\frac{dy}{dx}=f(x, y)$ is specified by, (choose one of the following). $y_{n+1}=y_n+hf(x_n, y_n)$ $y_{n+1}=y_n+hf(x_{n+1}, y_{n+1})$ $y_{n+1}=y_{n-1}+2hf(x_n, y_n)$ $y_{n+1}= (1+h)f(x_{n+1}, y_{n+1})$
Kathleen
asked
in
Numerical Methods
Oct 4, 2014
by
Kathleen
1.1k
views
gate1994
numerical-methods
backward-euler-method
out-of-gate-syllabus
0
votes
0
answers
43
GATE CSE 1993 | Question: 20
Kathleen
asked
in
CO and Architecture
Sep 29, 2014
by
Kathleen
569
views
gate1993
co-and-architecture
8085-microprocessor
out-of-gate-syllabus
0
votes
0
answers
44
GATE CSE 1997 | Question: 4.3
Using the forward Euler method to solve $y’'(t) = f(t), y’(0)=0$ with a step size of $h$, we obtain the following values of $y$ in the first four iterations: $0, hf (0), h(f(0) + f(h)) \text{ and }h(f(0) - f(h) + f(2h))$ $0, 0, h^2f(0)\text{ and } 2h^2 f(0) + f(h)$ $0, 0, h^2f(0) \text{ and } 3h^2f(0)$ $0, 0, hf(0) + h^2f(0) \text{ and }hf (0) + h^2f(0) + hf(h)$
Kathleen
asked
in
Numerical Methods
Sep 29, 2014
by
Kathleen
667
views
gate1997
numerical-methods
non-gate
out-of-gate-syllabus
0
votes
0
answers
45
GATE CSE 2000 | Question: 14
Consider the line $y=\frac{n}{m}x$, where $n$ and $m$ are positive integers. If mq - np < 0, then is the point (p,q) above the line, below the line, or on the line? Complete the following function, that returns true if the line segment with endpoints (p,q) and (r,s) ... *r)⊏⊐ 0 then clash:= true; 7: if(m*q - n*p)⊏⊐ 0 and (m*s - n*r)⊏⊐ 0 then clash:= true; 8: end;
Kathleen
asked
in
Others
Sep 14, 2014
by
Kathleen
692
views
gatecse-2000
descriptive
0
votes
0
answers
46
GATE CSE 1993 | Question: 02.8
Given $\vec v= x\cos ^2y \hat i + x^2e^z\hat j+ z\sin^2y\hat k$ and $S$ the surface of a unit cube with one corner at the origin and edges parallel to the coordinate axes, the value of integral $\int^1 \int_s \vec V. \hat n dS$ is __________.
Kathleen
asked
in
Calculus
Sep 13, 2014
by
Kathleen
957
views
gate1993
calculus
normal
out-of-gate-syllabus
fill-in-the-blanks
0
votes
0
answers
47
GATE CSE 1993 | Question: 02.4
Kathleen
asked
in
Numerical Methods
Sep 13, 2014
by
Kathleen
372
views
gate1993
numerical-methods
runga-kutta-method
out-of-gate-syllabus
fill-in-the-blanks
1
vote
0
answers
48
GATE CSE 1993 | Question: 02.2
The radius of convergence of the power series$\sum_{}^{\infty} \frac{(3m)!}{(m!)^3}x^{3m}$ is: _____________
Kathleen
asked
in
Calculus
Sep 13, 2014
by
Kathleen
1.2k
views
gate1993
calculus
convergence
normal
out-of-gate-syllabus
fill-in-the-blanks
2
votes
0
answers
49
GATE CSE 1992 | Question: 06,a,b
A microprocessor is capable of addressing 1 megabyte of memory with a 20-bit address bus. The system to be designed requires 256 K bytes of RAM, 256 K bytes of EPROM, 16 I/O devices (memory mapped I/O) and 1 K byte of ... to two clock cycles for memory read and write. Assuming control signals similar to 8085, design the extra logic required for interfacing EERAM.
Kathleen
asked
in
Digital Logic
Sep 13, 2014
by
Kathleen
1.0k
views
gate1992
digital-logic
descriptive
memory-interfacing
out-of-gate-syllabus
8085-microprocessor
2
votes
0
answers
50
GATE CSE 1991 | Question: 07a
It is required to design a hardwired controller to handle the fetch cycle of a single address CPU with a $16$ bit instruction-length. The effective address of an indexed instruction should be derived in the fetch cycle itself. ... bits of an instruction constitute the operand field. Give the register transfer sequence for realizing the above instruction fetch cycle.
Kathleen
asked
in
CO and Architecture
Sep 12, 2014
by
Kathleen
690
views
gate1991
co-and-architecture
control-unit
hardwired-controller
normal
unsolved
descriptive
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