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User amarVashishth
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Answers by amarVashishth
11
votes
1
GATE CSE 2009 | Question: 52
A hard disk has $63$ sectors per track, $10$ platters each with $2$ recording surfaces and $1000$ cylinders. The address of a sector is given as a triple $\langle c, h, s \rangle$, where $c$ is the cylinder number, $h$ is the surface number and $s$ is the sector ... $\langle 0, 16, 30 \rangle$ $\langle 0, 16, 31 \rangle$ $\langle 0, 17, 31 \rangle$
answered
in
Operating System
Jan 4, 2017
10.4k
views
gatecse-2009
operating-system
disk
normal
3
votes
2
GATE CSE 2008 | Question: 63
The $P$ and $V$ operations on counting semaphores, where s is a counting semaphore, are defined as follows: $P(s):$ $s=s-1;$ If $s < 0$ then wait; $V(s):$ $s=s+1;$ If $s \leq0$ then wake up process waiting on s; Assume that $P_b$ and $V_b$ the wait ... $x_b$ and $y_b$ are respectively $0$ and $0$ $0$ and $1$ $1$ and $0$ $1$ and $1$
answered
in
Operating System
Dec 28, 2016
22.9k
views
gatecse-2008
operating-system
normal
semaphore
0
votes
3
operating systems
system call is a)hardware interrupts b)software interrupt c)exception d)none o these i feel all a,b,c :(
answered
in
Operating System
May 3, 2016
737
views
1
vote
4
operating systems
a system has 6 processes sharing 7 resourses if each process needs maximum 3 units then a) deadlock can never occur b)deadlock may occur c)starvation will occur d)none of these
answered
in
Operating System
May 3, 2016
1.5k
views
4
votes
5
FOUR PROCESSES P1,P2,P3,P4 HAS RESOURSE R1,R2
FOUR PROCESSES P1,P2,P3,P4 HAS RESOURSE R1,R2 AS ,<4,3>,<2,4>,<3,6>,<2,8> WHAT SHOULD BE THE MINIMUM INSTANCES OF R1 AND R2 TO ENSURE THAT IT IS DEAD LOCK FREE???? CAN ANYONE EXPLAIN ME BRIEFLY HOE TO SOLVE THIS PROBLEM GIVE EXPLANATION TO U R ANSWER THE ANSWER IS <8,18>
answered
in
Theory of Computation
May 3, 2016
1.9k
views
45
votes
6
GATE CSE 2006 | Question: 79
Barrier is a synchronization construct where a set of processes synchronizes globally i.e., each process in the set arrives at the barrier and waits for all others to arrive and then all processes leave the barrier. Let the number of processes ... at the beginning of the barrier and re-enabled at the end. The variable process_left is made private instead of shared
answered
in
Operating System
Apr 29, 2016
8.3k
views
gatecse-2006
operating-system
process-synchronization
normal
50
votes
7
GATE CSE 2006 | Question: 81
A CPU has a $32$ $KB$ direct mapped cache with $128$ byte-block size. Suppose $A$ is two dimensional array of size $512 \times512$ with elements that occupy $8-bytes$ each. Consider the following two $C$ code segments, $P1$ and $P2$. $P1$: for (i=0; i<512; i++) { for ( ... $M2$. The value of the ratio $\frac{M_{1}}{M_{2}}$: $0$ $\frac{1}{16}$ $\frac{1}{8}$ $16$
answered
in
CO and Architecture
Apr 29, 2016
10.4k
views
co-and-architecture
cache-memory
normal
gatecse-2006
85
votes
8
GATE CSE 2007 | Question: 85
Suppose that a robot is placed on the Cartesian plane. At each step it is allowed to move either one unit up or one unit right, i.e., if it is at $(i,j)$ then it can move to either $(i + 1, j)$ or $(i,j + 1)$. Suppose that the robot is not allowed to traverse the ... $^{20}\mathrm{C}_{10} - ^{8}\mathrm{C}_{4}\times ^{11}\mathrm{C}_{5}$
answered
in
Combinatory
Apr 29, 2016
9.4k
views
gatecse-2007
combinatory
normal
discrete-mathematics
79
votes
9
GATE CSE 2010 | Question: 53
A hash table of length $10$ uses open addressing with hash function $h(k) = k \: \mod \: 10$, and linear probing. After inserting $6$ ... of the key values using the same hash function and linear probing will result in the hash table shown above? $10$ $20$ $30$ $40$
answered
in
DS
Apr 29, 2016
27.0k
views
data-structures
hashing
normal
gatecse-2010
1
vote
10
Question on shift reduce parsing
Given solution: After reducing two 1's of expression to E, E*E should be reduced not the 3rd 1. So final output will be 112*311+2 instead of the given output. Please check.
answered
in
Compiler Design
Jan 19, 2016
1.8k
views
compiler-design
parsing
test-series
2
votes
11
MadeEasy Test Series: Digital Logic - Digital Counter
The number of Clock pulses needed to change the contents of an 8-bit-up-counter from (10101011) to (00111010) is ______________
answered
in
Digital Logic
Jan 14, 2016
1.0k
views
made-easy-test-series
digital-logic
digital-counter
31
votes
12
GATE CSE 2004 | Question: 71
How many solutions does the following system of linear equations have? $-x + 5y = -1$ $x - y = 2$ $x + 3y = 3$ infinitely many two distinct solutions unique none
answered
in
Linear Algebra
Jan 13, 2016
8.3k
views
gatecse-2004
linear-algebra
system-of-equations
normal
1
vote
13
Find NID and Host ID bits, given destination address & mask to apply.
from MadeEasy test series.
answered
in
Computer Networks
Jan 9, 2016
3.0k
views
computer-networks
3
votes
14
Find RAW Dependencies
What is correct? $3 \text{ RAW dependencies}$ or
answered
in
CO and Architecture
Jan 8, 2016
932
views
co-and-architecture
0
votes
15
Asymptotics
Find the False statement. $O(2^n) = O(3^n)$ $O(\log n^2) = O(\log n)$ $f(n) = O \left ( (f(n))^2 \right )$ $2^{2 \log n} (\log n) = O(n^2 \log n)$
answered
in
Algorithms
Jan 7, 2016
811
views
algorithms
asymptotic-notation
19
votes
16
GATE CSE 1992 | Question: 4-a
Consider addition in two's complement arithmetic. A carry from the most significant bit does not always correspond to an overflow. Explain what is the condition for overflow in two's complement arithmetic.
answered
in
Digital Logic
Dec 30, 2015
2.6k
views
gate1992
digital-logic
normal
number-representation
descriptive
36
votes
17
GATE CSE 1991 | Question: 03,xii
If $F_1$, $F_2$ and $F_3$ are propositional formulae such that $F_1 \land F_2 \rightarrow F_3$ and $F_1 \land F_2 \rightarrow \sim F_3$ are both tautologies, then which of the following is true: Both $F_1$ and $F_2$ are tautologies The conjunction $F_1 \land F_2$ is not satisfiable Neither is tautologous Neither is satisfiable None of the above
answered
in
Mathematical Logic
Dec 30, 2015
8.7k
views
gate1991
mathematical-logic
normal
propositional-logic
multiple-selects
3
votes
18
GATE CSE 1991 | Question: 13
Give an optimal algorithm in pseudo-code for sorting a sequence of $n$ numbers which has only $k$ distinct numbers ($k$ is not known a Priori). Give a brief analysis for the time-complexity of your algorithm.
answered
in
Algorithms
Dec 30, 2015
6.6k
views
gate1991
sorting
time-complexity
algorithms
difficult
descriptive
3
votes
19
GATE CSE 1991 | Question: 01,xi
The arithmetic expression $(a+b) * c- d/e ** l$ is to be evaluated on a two address machine, where each operand is either a register or a memory location. With a minimum number of memory accesses of operands.the number of registers required to evaluate this expression is ______. The number of memory accesses of operands is ____________
answered
in
Compiler Design
Dec 30, 2015
1.7k
views
gate1991
compiler-design
register-allocation
out-of-gate-syllabus
10
votes
20
GATE CSE 1991 | Question: 15,b
Consider the following first order formula: ... Does it have finite models? Is it satisfiable? If so, give a countable model for it.
answered
in
Mathematical Logic
Dec 30, 2015
6.3k
views
gate1991
mathematical-logic
first-order-logic
descriptive
2
votes
21
probability
Three numbers are chosen at random without replacement from $\left\{1, 2, 3,....., 10 \right\}$. What is the probability that minimum of the chosen numbers is $3$ or their maximum is $7$? $\frac{11}{30}$ $\frac{11}{40}$ $\frac{1}{7}$ $\frac{1}{8}$
answered
in
Probability
Dec 26, 2015
2.1k
views
probability
engineering-mathematics
2
votes
22
Solve
At $t=0$, the function $f(t)=\frac{\sin t}{t}$ has (A) a minimum (B) a discontinuity (C) a point of inflection (D) a maximum
answered
in
Calculus
Dec 26, 2015
2.8k
views
maxima-minima
68
votes
23
GATE CSE 2015 Set 2 | Question: 6
With reference to the B+ tree index of order $1$ shown below, the minimum number of nodes (including the Root node) that must be fetched in order to satisfy the following query. "Get all records with a search key greater than or equal to $7$ and less than $15$ " is ______.
answered
in
Databases
Dec 26, 2015
13.2k
views
gatecse-2015-set2
databases
b-tree
normal
numerical-answers
1
vote
24
Pipeline
please draw chart for this question
answered
in
CO and Architecture
Dec 26, 2015
951
views
58
votes
25
GATE CSE 1999 | Question: 2.2
Two girls have picked $10$ roses, $15$ sunflowers and $15$ daffodils. What is the number of ways they can divide the flowers among themselves? $1638$ $2100$ $2640$ None of the above
answered
in
Combinatory
Dec 26, 2015
12.1k
views
gate1999
combinatory
normal
45
votes
26
GATE CSE 1999 | Question: 13
An instruction pipeline consists of $4$ stages - Fetch $(F)$, Decode field $(D)$, Execute $(E)$ and Result Write $(W)$. The $5$ instructions in a certain instruction sequence need these stages for the different number of clock cycles as shown by the ... $5$ instructions.
answered
in
CO and Architecture
Dec 25, 2015
10.4k
views
gate1999
co-and-architecture
pipelining
normal
numerical-answers
10
votes
27
GATE CSE 2015 Set 2 | Question: 44
Consider the sequence of machine instruction given below: ... forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instruction is _________.
answered
in
CO and Architecture
Dec 25, 2015
26.3k
views
gatecse-2015-set2
co-and-architecture
pipelining
normal
numerical-answers
26
votes
28
GATE IT 2006 | Question: 79
A pipelined processor uses a 4-stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the EX ... is used. The number of clock cycles required to complete the sequence of instructions is $10$ $12$ $14$ $16$
answered
in
CO and Architecture
Dec 25, 2015
17.3k
views
gateit-2006
co-and-architecture
pipelining
normal
25
votes
29
GATE CSE 2005 | Question: 68
A $5$ stage pipelined CPU has the following sequence of stages: IF - instruction fetch from instruction memory RD - Instruction decode and register read EX - Execute: ALU operation for data and address computation MA - Data memory access - for write access, the ... taken to complete the above sequence of instructions starting from the fetch of $I_1$? $8$ $10$ $12$ $15$
answered
in
CO and Architecture
Dec 25, 2015
46.0k
views
gatecse-2005
co-and-architecture
pipelining
normal
60
votes
30
GATE CSE 2001 | Question: 12
Consider a $5-$stage pipeline - IF (Instruction Fetch), ID (Instruction Decode and register read), EX (Execute), MEM (memory), and WB (Write Back). All (memory or register) reads take place in the second phase of a clock cycle ... Show all data dependencies between the four instructions. Identify the data hazards. Can all hazards be avoided by forwarding in this case.
answered
in
CO and Architecture
Dec 24, 2015
17.3k
views
gatecse-2001
co-and-architecture
pipelining
normal
descriptive
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