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1
GATE CSE 2021 Set 2 | Question: 54
Consider a network using the pure $\text{ALOHA}$ medium access control protocol, where each frame is of length $1,000$ bits. The channel transmission rate is $1$ Mbps ($=10^6$ bits per second). The aggregate number ... the average number of frames successfully transmitted per second. The throughput of the network (rounded to the nearest integer) is ______________
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in
Computer Networks
Feb 26, 2021
13.9k
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gatecse-2021-set2
computer-networks
mac-protocol
pure-aloha
numerical-answers
2-marks
2
answers
2
william stallings computer organization control unit
Assume that the control memory is 24 bits wide. The control portion of the microinstruction format is divided into two fields.A micro-operation field of 11 bits specifies the micro-operations to be performed. An address selection field specifies a ... b. How many bits are in the address field? c. What is the maximum size of the control memory?
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in
CO and Architecture
Feb 6, 2021
2.6k
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control-unit
co-and-architecture
2
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3
GATE CSE 2001 | Question: 12
Consider a $5-$stage pipeline - IF (Instruction Fetch), ID (Instruction Decode and register read), EX (Execute), MEM (memory), and WB (Write Back). All (memory or register) reads take place in the second phase of a clock cycle ... Show all data dependencies between the four instructions. Identify the data hazards. Can all hazards be avoided by forwarding in this case.
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CO and Architecture
Jan 22, 2021
17.3k
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gatecse-2001
co-and-architecture
pipelining
normal
descriptive
12
answers
4
GATE CSE 2005 | Question: 80
Consider the following data path of a $\text{CPU}.$ The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including incrementation of the $\text{PC}$ and the $\text{GPRs}$ are to be carried out in ... $2$ $3$ $4$ $5$
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CO and Architecture
Jan 15, 2021
24.1k
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co-and-architecture
normal
gatecse-2005
data-path
machine-instruction
3
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5
Self Made: Hit Latency
Cache 1 Direct Mapping 17 tag 10 block 5 word Cache 2 Set Assosicative 2- way associative 18 9 5 Cache 3 Associative Cache 27 5 Calculate Hit Latenncy in Each of Three Cache Memory if 2 to 1 MUX / OR has latency of 0.6ns k-bit comparator has katency of k/10 ns 2.How much number of MUX / OR ? camparators are used in each of three
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CO and Architecture
Dec 19, 2020
6.8k
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co-and-architecture
cache-memory
hit-latency
self-made
7
answers
6
GATE CSE 2000 | Question: 1.21
Let $m[0]\ldots m[4]$ be mutexes (binary semaphores) and $P[0]\ldots P[4]$ be processes. Suppose each process $P[i]$ executes the following: wait (m[i]); wait (m(i+1) mod 4]); ........... release (m[i]); release (m(i+1) mod 4]); This could cause Thrashing Deadlock Starvation, but not deadlock None of the above
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in
Operating System
Nov 21, 2020
21.9k
views
gatecse-2000
operating-system
process-synchronization
normal
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