GATE CSE 2005 | Question: 79

Question

Consider the following data path of a $\text{CPU}.$

The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including incrementation of the $\text{PC}$ and the $\text{GPRs}$ are to be carried out in the $\text{ALU}.$ Two clock cycles are needed for memory read operation – the first one for loading address in the $\text{MAR}$ and the next one for loading data from the memory bus into the $\text{MDR}.$

The instruction $``\text{add R0, R1}”$ has the register transfer interpretation $\text{R0} \Leftarrow \text{R0 + R1}.$ The minimum number of clock cycles needed for execution cycle of this instruction is:

• A. $2$
• B. $3$
• C. $4$
• D. $5$

Comments

In the ques. it is given that one cycle for loading data to MAR and second for read the data from MBR. so firstly we need to fetch the data from memory for which itself requires 4 cycle for both registers bcoz 2 for MAR and MDR for r0 and similarly for r1. so how come the ans. will be 3? plz explain clearly....

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@purubgp

No ,it is total 2 clock cycles are needed for memory read operation , 1 clock cycle for MAR ( memory address register ) another clock cycle for MDR ( memory data register ) . But this is part of Instruction cycle , not the execution cycle.

For execution there is 3 cycles only . Question asks minimum number of clock cycles needed for execution cycle .

1 clock cyle for R0 to S

2nd clock cycle for R1 to T

3rd clock cycle for add operation means R0 + R1 .

so for execution only 3 cycles require .

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if anyone comes up with a better explanation then please post it.As all explanations are confusing

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3??

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Yes, please explain

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1 cycle to place R0 into S

1 cycle to place R1 into T

1 cycle R0<-S+T

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won't it be like 2 cycles for reading R0 and 2 cycles for R1 and the 1 cycle for add. It's mentioned two cycles for memory read operation.

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The question ask for minimum number of clock cycles during the execution cycle of this instructions
1 clock cycle for Add operation
1 clock cycle for selecting destination register using MAR
1 clock cycle for storing data in destination register using MDR.

Total 3 clock cycles.

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Gupta731 whats ur question

The minimum number of clock cycles needed for execution of this instruction is

or

The minimum number of CPU clock cycles needed during the execution cycle of this instruction is

 

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i think first part

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they just confuse us with instruction cycle and execution cucle

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https://gateoverflow.in/1402/gate2005-79

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yeah I got it.

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kya kya socha tha last mein kya nikla R0 to S, R1 to T, R0=R0+R1,

total 3 cycle ho gaya

vaah!

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during the instruction fetch

first the content of PC is moved to MAR (MAR ← PC) then PC is incremented in the ALU for this the content of PC is copied in one of S or T (S ← PC) and then (PC ← S + 1) after this the data from the mem address is copied into the MDR( MDR← mem[MAR]) then from MDR it is copied to the IR(IR← MDR) . so the total cycles required should be 3 cycles.

where am i going wrong?

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Carl Hamacher and William Stallings describes Fetch phase to be completed in 3 cycles. So according to these books your sequence in correct. But in Morris Mano, Fetch phase takes 2 clock cycle,

1.  PC -->MAR
2. [MAR]-->IR

So, it depends. that’s why they asked for execution phase only.

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i just wanna know why alu cycle is not take here. why directly add and store in register

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@manikantsharma

But, here it is mentioned that value of $PC$ is incremented in the ALU.

Doubt:

There is not need to copy the $PC$ value in the $MDR$ right? as it is just for data, and $MAR$ value can be directly transffered into $IR$, which means that the instruction fetch is completed.

am i correct?

Answer 1

Instruction fetch requires two cycles but the question asks for the execution part only!

Now for execution:

1. $R1_{out}, S_{in}\qquad S \leftarrow R0 \quad -1^{st}$ cycle
2. $R2_{out}, T_{in}\qquad T \leftarrow R1 \quad - 2^{nd}$ cycle
3. $S_{out}, T_{out}, \text{Add } R0_{in} \quad R0 \leftarrow R0 + R1  \quad -  3^{rd}$ cycle

So, $3$ cycles for execution.

As it is asked for only execution cycles, no of cycles required $=3.$

Had it been asked for instruction cycles, then the answer will be $5.$

Hence, option B is correct.

Comments

why is not a cycle from ALU → R0 not considered, or maybe ALU gives output back to S but then we need to supply back S to R0 ( Write back stage) ?? shouldn’t it be 4 cycles.

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An instruction cycle is consisting of

1) Fetch Cycle

2)Decode cycle

3)Execution cycle

and in this question, they have asked for Execution Cycle Only.

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execution cycle = OF + compute + WB.

2 cycle for OF, 1 cycle for WB but why we not taking 1 cycle for computation(addition)

Answer 2

S <- R0 ...... 1cycle ( Since the buses are of same size as the

T <- R1 ...... 2nd cycle

R0 <- R0 + R1  ..... 3rd cycle

therefore we need 3 cycles.

Comments

will operand fetch not be the part of execution ?

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If One wonders why S <- R0 is one cycle. 

It is given,

"Two clock cycles are needed for memory read operation – the first one for loading address in the MAR...."

Means PC to MAR one cyle, and it is given all registers are same size. so  R0 to S also one cycle.

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because its register to register operation which doesnt involve memory read operation. We are assuming that operands are present in R0 and R1 already.

Answer 3

All the answers here are a tad confusing, I want to share my solution with evidences from the book "Computer Organisation and Embedded System" by Hamacher et al

In the book it is clearly mentioned that

Instruction processing consists of two phases: the fetch phase and the execution phase. It is convenient to divide the processor hardware into two corresponding sections. One section fetches instructions and the other executes them.

The section that fetches instructions is also responsible for decoding them and for generating the control signals that cause appropriate actions to take place in the execution section. The execution section reads the data operands specified in an instruction, performs the required computations, and stores the results.

Considering this in mind we can approach this question with each stage in the Execution cycle to be taking 1 clock cycle each, that is :

Execution Cycle : OF + Compute + WB

OF : 1 clock cycle for S_in←R0 and T_in←R1 both (as both can be done parellely)

Compute : 1 clock cycle for ALU_out←S+T

WB : 1 clock cycle for writing the result R0_in←ALU_out

So in total 3 clock cycles are needed for the Execution cycle.

P.S - We don't have to assume anything at our end until and unless it is explicitly stated in the question, and the statement 

The instruction “add R0, R1” has the register transfer interpretation

doesn't mean that only register operations are to be considered for the clock cycle but it is providing the interpretation for the instruction to be R0 <= R0 + R1 and nothing else, please don't misinterpret it.

Comments

How S_in←R0 and T_in←R1  can run in parallel...when the bus is in control of S then how it can be given to T at the same time.

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Loading S and T parallely ? How?

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It means for addition it doesn't require one cycle  ALU operation doesn't require any cycle but for storing the result in register it requires one cycle.

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Sin←R0 and Tin←R1   cannot be done parallely.

Answer 4

R₀  <= R₀ +R₁

The sequence of instruction take place 

I Cycle : R_{1 out}  , S_in

II Cycle: Ro _{out  ,} T_in

III Cycle: S_{out  ,}   T_{out ,} ALU , R_{in therefore 3 cycle required} 

Comments

whats the diff btw execution cycle and instruction cycle??

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@akriti sood, Instruction Cycle for fetching of instruction and execution cycle is for execution of instructions. Also, at the same time instructions/operands may be fetched. :). Hope you get it.

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Instruction cyle means

1. Fetch cycle
2. Execution cycle 

• PC to MAR
• M[MAR] to MBR,PC+STEPSIZE
• MBR to IR