Let's Check all the conditions one by one, shall we?
1. Race around condition occurs in a SR f/f When both the input S=R=1.
Race around condition basically means both Set and Reset keeps on toggling each other for indefinite amount of time 0101010101.....(infinite), however this may stand TRUE for SR Latch constructed using NOR Gate, but for NAND implementation of SR Latch also called( S'R' Latch) The race condition will be S=R=0
However, the question asks for SR Latch so I am assuming it (TRUE)
2. A transparent latch consist of a D F/F.
Transparent Latch means, when Enable=1 in D Latch, the Data input goes in to the latch and when Enable=0 in D Latch, the Data Get's stored within the Latch,which is later shown as output. Hence it can act as temporary binary storage.
(TRUE)
3. Edge triggered f/f removes the race condition.
Edge triggered flip flop, basically consists of 2 flip flops, Master and Slave Jk or even D flip flops, here, the input to slave is complemented using and Inverter and hence Race Condition is avoided!
(TRUE)
4.Master slave configuration is used in f/f to store two bits of information.
As mentioned before in master slave configuration, only 1 flip flop is active at a time to avoid race condition, and one flip flop stores one bit of binary information. so as soon as one of the two becomes active, the transparency comes into affect and the contents of the fist flip flop are presented as output!
(False)
Answer :1,2,3
