Made easy CA q17

Question

The time delays of 4 segments are 60 ns, 70 ns, 100 ns and 80 ns respectively. Interface registers are have the delay of 10 ns.  what is the speed up?

a.  2.9      b. 2.6       c. 3.2       d. 1.8

Answer 1

S= t_n/ t_p = S1 + S2 +S3 + S4 / max (S1+10 , S2+10, S3+10, S4+10)
              =60+70+100+80/max(60+10, 70+10, 100+10,80+10)

             = 310/110=2.818
             ≃2.9 option A
 

Comments

one doubt, in pipeline is their any need of adding the buffer in the last stage??

Answer 2

T_n = Time to execute N instructions in a non-pipelined design

=60 + 70 +100 + 80 + 10 = 320

T_p= Time to execute N instructions in a pipelined design

=100 +10 =110

Speed Up = T_n / T_p

                  = 320 / 110 =2.9

Comments

Do we need interface register in non-pipe?
what is the use of Interface register in Non-pipeline?

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if in the question they have mention the buffer delay or interstage delay then we have to consider it . Interface register is used for interstage transfer of data (Buffer overhead) and it is same for all the stages.

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inter stage transfer is done none pipeline to if yes then why you are adding only one inter register delay there are 4 stages?

Answer 3

Speed Up = Time Without Pipeline / Time With Pipeline

                 = (60 +70 + 100 + 80) / max(60,70,100,80) + 10

                 = 310/ 110 

                 = 2.8

You might get a doubt why we did not included interstage buffer delay in Non Pipeline. It is because it is used in pipeline for operand forwarding from one stage to other. But in Non Pipeline since we are executing one instruction at a time. So there is no operand forwarding and therefore not required.