self doubt(NPTEL assignment)

Question

Encode the instruction sub r1, r2, 3

 (a) 00001 0 0001 0010 00 0000 0000 0000 0011

 (b)00001 1 0001 0010 00 0000 0000 0000 0011

(c) 00011 1 0001 0010 00 0000 0000 0000 0111

 (d)None of the above

Comments

with out knowing the SUB instruction implement ( how many instructions are there in your Instruction Set Architecture and etc..), and how many registers you have.. we can't answer this type of questions

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As @Shaik pointed it out, this is specific to the Instruction Set Architecture of the processor. Without knowing the opcodes for SUB and the memory location of R1 and R2, it is not possible.

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in question  only above information is given.

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If that's the case, the question is incorrect.