stage delays doubt in pipelining

Question

if a instruction pipeline has 5 stages with different stage delays 2 , 3 , 4 , 5, 6 ns . The pipeline registers are required between each stage and at the end of last stage. each register delay is 1ns.

How the time taken by a NON-PIPELINED implementation is calculated for n no. of instructions? and what is the speed up here?

Comments

In non pipeline arch we will not consider the buffer registers, so time taken for each instruction is 20ns(2+3+4+5+6)

whereas in pipelined arch, maximum of stage delay + single buffer delay is taken ==>6+1=>7ns for one clk

Speed up =$\frac{time without pipeline}{Time with pipeline}$

                  =$\frac{n*20}{5*7+(n-1)*7}$

                   =$\frac{20n}{35+7n-7}$

                   =$\frac{20n}{7n-28}$

                   =$\frac{20n}{7n}$  (assuming a very large n)

                   =2.86

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Where is the number 10 coming from?

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it think it should be 20( = 6+5+4+3+2)

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Corrected it :)

Answer 1

In non-pipelined we dont consider the buffer delay,

so time required for 1 instruction in non pipelined system = 2+3+4+5+6=20ns

For n instructions =n*20

Time required in Pipelined system = 5*(7)+(n-1)*7=7n-28

Now, speed up = Time(non-pipelined)/Time(pipelined)

                         =20n/7n-28

For large value of n,= 20n/7n = 2.86