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Recent questions tagged cache-memory

2 votes

1 answer

241

ME TEST SERIES
A byte addressable computer has a small data cache capable of holding 16 32-bit words. Each cache block consist of four 32 bits words. For the following sequence of main memory addresses (in hexadecimal). The conflict miss if 2-way set associative LRU cache is used is ________. 100, 108, 114, 1C7, 128, 1B5, 100, 108, 1C7

himgta asked in CO and Architecture Dec 12, 2018

by himgta

1.9k views

0 votes

0 answers

242

conceptual doubt
in case of hierarchical memory organization when there is a miss in cache , we need to bring the entire block from main memory to cache so in the formula- AMAT= H1*T1+(1-H1(T1+T2)) T1- cache access time/word T2= memory access time/word T2 ... in some cases we just take word access time of main memory. also please tell me what should be T2 in case of simultaneous organization?

sushmita asked in CO and Architecture Dec 12, 2018

528 views

0 votes

0 answers

243

Cache indexing
What is the meaning of cache indexing?

Ajit J asked in CO and Architecture Dec 12, 2018

by Ajit J

235 views

0 votes

0 answers

244

made eassy test
consider a cache with 32 blocks and each block of size 32 byte. The byte address 1216 of main memory will map which line of cache

Harshit Bajpai asked in CO and Architecture Dec 11, 2018

by Harshit Bajpai

266 views

0 votes

0 answers

245

Stallings (write through)
Consider a cache with a line size of 32 bytes and a main memory that requires 30 ns to transfer a 4-byte word. For any line that is written at least once before being swapped out of the cache, what is the average number of times that the line must be written before being swapped out for a write-back cache to be more efficient that a write-through cache?

Ajit J asked in CO and Architecture Dec 10, 2018

by Ajit J

822 views

0 votes

0 answers

246

MadeEasy Test Series: CO & Architecture - Cache Memory
Consider a 2-level L1 and L2 memory hierarchy system. The associativity of L1 towards processor is more. L1 (cache) has accessing time of 15 ns and L2 (main memory) has an accessing time of 100 ns. Writing takes 30 ... the instruction are read only instructions. What is the average access time for the system if it uses write through protocol?

naveen bhatt asked in Operating System Dec 10, 2018

by naveen bhatt

571 views

0 votes

0 answers

247

GATE analysis
An Intel processor uses a cache block size of 128 bytes and a memory transfer to cache is about 10 times the access time of cache memory. with cache hit ratio of 0.97 what percent will be the effective memory access to that of access time of memory A. 20 percent B. 30 percent C. 40 percent D. 50 percent

Abhijit Borah asked in CO and Architecture Dec 10, 2018

by Abhijit Borah

453 views

0 votes

0 answers

248

aditi19 asked in CO and Architecture Dec 8, 2018

311 views

0 votes

1 answer

249

MadeEasy Test Series: CO & Architecture - Cache Memory
A : LRU replacement policy is not applicable to direct mapped caches B : A unique memory page is associated with every cache page in direct mapped caches Options: 1) Both True 2) Both False 3) A is True and B is false 4) B is True and A is false

jatin khachane 1 asked in CO and Architecture Dec 6, 2018

by jatin khachane 1

2.2k views

1 vote

1 answer

250

GA Test Series
answer is 1.. but I’m getting more than 1

aditi19 asked in CO and Architecture Dec 6, 2018

442 views

0 votes

0 answers

251

cache
Consider a system with the average memory access time of a processor with one level (L1) cache is 2.8 clock cycles. If the required data is present in L1-cache it can be accessed in 1 clock cycle otherwise it needs 85 clock cycles to get it from memory. If another ... the access time of 6 clock cycles. What is the hit rate of L2-cache such that average memory access improved by 70%? (ans=71%)

Satbir asked in CO and Architecture Dec 6, 2018

by Satbir

232 views

0 votes

0 answers

252

aditi19 asked in CO and Architecture Dec 6, 2018

530 views

0 votes

0 answers

253

MadeEasy Test Series: CO & Architecture - Cache Memory
why in the calculation , cache access time is not included on cache miss? correct answer is 32.5.

Ashwani Yadav asked in CO and Architecture Dec 6, 2018

by Ashwani Yadav

238 views

0 votes

0 answers

254

made easy
correct answer is 32.5 . why in the calculation, on cache miss, cache access time is not included?

Ashwani Yadav asked in CO and Architecture Dec 6, 2018

by Ashwani Yadav

152 views

0 votes

0 answers

255

Cache mapping Doubt
https://gateoverflow.in/494/gate2008-71 can someone explain how indexes of the array elements have been calculated?

aditi19 asked in CO and Architecture Dec 5, 2018

301 views

0 votes

1 answer

256

Hamacher 6th edition Q8.8
A block-set-associative cache consists of a total of 64 blocks, divided into 4-block sets. The main memory contains 4096 blocks, each consisting of 32 words. Assuming a 32-bit byte-addressable address space, how many bits are there in each of the Tag, Set, and word fields?

GAURAV_JAIN asked in CO and Architecture Dec 4, 2018

5.8k views

0 votes

0 answers

257

Made easy workbook

Gaurangi Katiyar asked in CO and Architecture Dec 2, 2018

by Gaurangi Katiyar

276 views

0 votes

1 answer

258

Tag directory size in associative mapped cache
What is the correct formula for tag directory size in associative mapped cache concept.?

Tulsidhar M asked in CO and Architecture Nov 30, 2018

807 views

0 votes

0 answers

259

no. of hits_RC test series
Assume that cache is 2 way set associative and has the following configurations:- (i) 8B of the total size (ii)2B of block size (iii)LRU replacement if byte-addressable memory has 16-bit addresses then find the number of hits for the following reference stream(initially the cache is empty) 2,3,5,7,12,1,2,4,13 am getting 4 hits but the answer given is different

Gate Fever asked in CO and Architecture Nov 28, 2018

351 views

0 votes

1 answer

260

directly mapped cache_raman classes test series
Consider a directly mapped cache in which the number of tag bits is equal to the number of words in the block and the number of words is equal to the number of blocks in the cache. If there are N blocks in the cache, what is the size of physical memory in words??

Gate Fever asked in CO and Architecture Nov 28, 2018

208 views

0 votes

0 answers

261

me test series
Consider Prof. Vamshias writes a program given below and runs on a system which has 2-way set associative 16 KB data cache with 32 bytes block where each word size is 32 bits and LRU replacement policy used. If the base address of the array is 0 and initially the cache is empty then the ... for(i=0;i<1024;i++) x +=a[i] + a[1024 * i]; I am getting 1151 but the answer given is 1279

Neeti priya asked in CO and Architecture Nov 28, 2018

163 views

0 votes

1 answer

262

Local Coaching
A cache is having 60% hit ratio. Cache access time is 30 ns and main memory access time is 100 ns. What is the average access time for reading? My doubt is whether to assume cache and main memory to be hierarchically connected or directly connected to the processor when nothing is given? If assumed ... , ans = 0.6(30) + 0.4(30+100). If assumed to be direct, ans = 0.6(30) + 0.4(100).

subho16 asked in CO and Architecture Nov 26, 2018

511 views

0 votes

0 answers

263

MADE EASY TEST SERIES
Consider a program given below and run on a system that has 2-way set associative 16KB data cache with 32 bytes block where each word size is 32 bits and LRU replacement policy is used. If the base address of A is 0 initially cache is empty then the number of data cache misses are there. int i , A[1024*1024], x=0; for(i=0;i<1024;i++) { x=x+A[i]+A[1024*i]; }

Jain Sagar asked in CO and Architecture Nov 26, 2018

336 views

0 votes

1 answer

264

Ace academy test series

amitqy asked in Operating System Nov 25, 2018

by amitqy

816 views

0 votes

1 answer

265

cache memory
Consider a two-level memory hierarchy, L1 (cache) has an accessing time of 5 ns and main memory has an accessing time of 100 ns. Writing or updating contents takes 20 ns and 200 ns for L1 and main memory respectively. Assume L1 gives misses 20% ... instructions being read-only instructions. What is the average access time for the system (in ns) if it uses the WRITETHROUGH technique?

Shivangi Parashar 2 asked in CO and Architecture Nov 25, 2018

by Shivangi Parashar 2

1.3k views

0 votes

1 answer

266

Cache Memory
consider two-level cache hierarchies with L1 and L2 cache. Programs refer to memory 1000 times out of which 40 misses are in the L1 cache and 10 misses are in the L2 cache.If the miss penalty of L2 is 200 clock cycles,hit time of L1 is 1 clock cycle,and hit time of L2 is 15 clock cycles,the average memory access time is__________clock cycles.

Shivangi Parashar 2 asked in CO and Architecture Nov 25, 2018

by Shivangi Parashar 2

1.2k views

0 votes

2 answers

267

ME Test Series
Consider a CPU containing 2000 instructions, there are 80 misses In the $L_1$ cache and 40 misses In the $L_2$ cache. Assume the miss penalty from the $L_2$ cache to memory is 200 clock cycles, the hit time of $L_2$ cache Is 30 clock cycles, ... time of $L_1$ cache Is 5 clock cycles and these are 1.8 memory references per instruction, then average stall per instruction Is _________.

Shadan Karim asked in CO and Architecture Nov 23, 2018

by Shadan Karim

595 views

0 votes

1 answer

268

Self-Doubt
Consider Main memory M and Cache C. 1. When we say the access time of main memory is T what parameters does it include?Is it . just obtaining data from M or .obt data from M and Transfer it to cache(I understood as this) or . Obt data from M, ... which scenario do we take? Pls, help me with these finer aspects. I understood the overall idea. In NATs, I'm missing by small margins.

Aravind Adithya 1 asked in CO and Architecture Nov 23, 2018

by Aravind Adithya 1

261 views

0 votes

1 answer

269

homework
Main disadvantage of direct mapping is that cache his ratio decreases sharply it two or more frequently used blocks map on to same region. For two level memory hierarchy cache and main memory, WRITE THROUGH results in more write cycles to main emeory then WRITE BACK. is it true or false ? with reasons ? thank you in advance

deepanshu sharma 3 asked in CO and Architecture Nov 17, 2018

by deepanshu sharma 3

462 views

2 votes

2 answers

270

Set way Associative

Na462 asked in CO and Architecture Nov 14, 2018

by Na462

644 views

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Recent questions tagged cache-memory