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Recent questions tagged cache-memory

2 votes

1 answer

271

Gateforum Test Series: CO & Architecture - Cache Memory
Isn't the answer 18 ns but 36 ns is provided as a valid answer.

Gupta731 asked in CO and Architecture Nov 12, 2018

326 views

0 votes

0 answers

272

Made easy test series
Consider a single level cache with an access time of 2.5ns, a line of 64B and a hit ratio of 0.95. Main memory uses a block transfer capability that has a first word i.e. 4B access time of 50ns and after that 5ns for each word access. If cache waits until block is copied from MM to the cache and then access from cache,the access time is________(in ns) (upto 3 decimal places)

Somoshree Datta 5 asked in CO and Architecture Nov 11, 2018

by Somoshree Datta 5

596 views

1 vote

2 answers

273

COA: Cache Accesss Time
Little confusion with these questions. What will be o/p for these two questions one with Write back and the other is Write through. 1.)A 128 word cache and main memory are divided into 8 word blocks. The access time of a cache ... average access time? What will be the default technique ( write-allocate and no write-allocate)followed for Hierarchal and Simultaneous access ?

Hemanth_13 asked in CO and Architecture Nov 7, 2018

778 views

0 votes

0 answers

274

made easy tt2
IS THE ANSWER 1.794??

Gate Fever asked in CO and Architecture Nov 3, 2018

552 views

0 votes

0 answers

275

made easy tt2
SHOULDN'T THE ANSWER BE 11,4,6 ???

Gate Fever asked in CO and Architecture Nov 2, 2018

213 views

0 votes

0 answers

276

Cache Memory
More than one word is put in one cache block to (a) Exploit temporal locality references in a program (b) Exploit spatial locality references in a program (c) Reduce miss penalty (d) All of these

Dhiraj Raj asked in CO and Architecture Nov 2, 2018

363 views

0 votes

0 answers

277

Gateforum Test Series

Gupta731 asked in CO and Architecture Nov 1, 2018

383 views

0 votes

1 answer

278

ACE TESTSERIES
WHAT WILL BE THE ANS I M GETTING 10 BITS IN TAG FIELD!!! IS IT CORRECT THEY SHOWS DIFFERENT ANS NOT 10!! ANYONE TRY PLEASE AND LET ME KNOW THANKS IN ADVANCE!!

CHïntän ÞäTël asked in CO and Architecture Oct 25, 2018

by CHïntän ÞäTël

314 views

0 votes

0 answers

279

cache memory doubt
#CO Suppose Cache memory with K way set associative mapping,with no. of set -S,no. of line -L,size of each line -O. so what is hardware requirement (i.e.No.of multiplexer ,size of each multiplexer,no.of comparator,and size of each comparator) ?

Tanmay_Jawkhede asked in CO and Architecture Oct 20, 2018

by Tanmay_Jawkhede

210 views

0 votes

2 answers

280

Set associative mapping
What is the number of multiplexers required in set associative mapping hardware ? Given set bits are S, tag bits are T and word bits are W.

Alakhator asked in CO and Architecture Oct 19, 2018

676 views

0 votes

1 answer

281

Gate forum workbook
We are Simulate a cache of 16 words, 2-way set associate cache with 2 word cache lines and LRU replacement policy; assume the cache in initially empty. The following sequences of address references are generated (the addresses are given in hexadecimal), where all references are instruction ... (A) Set 1 contains 6A (B) Set 0 contains 108 (C) Both (A) and (B) (D) None of these

pream sagar asked in CO and Architecture Oct 19, 2018

359 views

0 votes

0 answers

282

Gate forum work book
Assume that we have three scenarios l. a fully associative cache, 2. a two way set associative cache and 3. a direct mapped cache. The cache size is 256 bytes. The cache line size is 8 bytes. All variables are 4 bytes. Assume that we have separate instruction and ... many data cache read misses will occur in Two-ay set associative cache? (A)11 (B) 19 (C) 35 (D) None of these

pream sagar asked in CO and Architecture Oct 19, 2018

419 views

0 votes

0 answers

283

self doubt
what is the principle of inclusion in cache . pleasse explain in simple terms

Deepanshu asked in CO and Architecture Oct 15, 2018

268 views

0 votes

2 answers

284

cache memory
Number of sets = 128 2 way set Associative Cache size = 4Kbytes Main memory has 21 bit address What are the sizes of the cache blocks and number of cache blocks respectively?

altamash asked in CO and Architecture Oct 12, 2018

837 views

3 votes

0 answers

285

MadeEasy Test Series: CO & Architecture - Cache Memory

Shubhanshu asked in CO and Architecture Oct 12, 2018

851 views

1 vote

2 answers

286

garimanand asked in CO and Architecture Oct 8, 2018

397 views

0 votes

1 answer

287

When to use word access time and when to use block access time in access time calculation.
Hello, I came across this question when practicing from a gate app. My question is here simultaneous access is used and hence we are transferring from cache to cpu if hit or main memory to ... is needed. Added the image of question. Thanks https://gateoverflow.in/?qa=blob&qa_blobid=13957411914537045045

Chaitrasj asked in CO and Architecture Oct 4, 2018

196 views

0 votes

1 answer

288

ACE TEST SERIES QUESTION

Shankar Kakde asked in CO and Architecture Oct 1, 2018

by Shankar Kakde

282 views

4 votes

2 answers

289

Na462 asked in CO and Architecture Oct 1, 2018

by Na462

815 views

0 votes

0 answers

290

DIRECT CACHE
https://gateoverflow.in/863/gate2002-10 IN THE SOLUTION BY ARJUN SIR HOW THIS LINE IS JUSTIFYING THAT ALL WILL MAP TO DIFFERENT SET?????? So, since the ending address is not extending beyond these 9 bits,9 bits, all cache accesses are to diff sets.

eyeamgj asked in CO and Architecture Oct 1, 2018

216 views

0 votes

0 answers

291

Self-doubt What events happen in Cache Access duration
What events happen when we say that a cache at level i is accessed? (I am able to use the cache formulas as given in textbooks and also most of the times, I arrive at the correct answer, but I want to fully understand the basic details ... duration? Do we include any extra time for STORING the data in the level (i-1)th cache as is done here ?

Harsh Kumar asked in CO and Architecture Sep 29, 2018

267 views

0 votes

0 answers

292

Self-doubt Cache Access Time theory
What events happen when we say that a cache at level i is accessed. My understanding is the following events occur in the duration of an access time: The level i cache memory's RAM is accessed using the data bus. The cache RAM loads the required ... duration? Do we include any extra time for STORING the data in the level (i-1)th cache as is done here ?

Harsh Kumar asked in CO and Architecture Sep 29, 2018

174 views

0 votes

0 answers

293

Load Back Cache
In the memory access time formula for the hierarchical cache - which is given as :$Emat = H1\times T1 + (1-H1)(H2\times (T1+T2) + (1-H2)\times (T1+T2+T3))$ (where Hi = Hit Ratio for the i-th level cache and Ti = Access time for i- ... transferred into the cache. Is my intuition correct? If yes, then what should be the Emat formula for Load Back cache ? Should we add extra Ti values?

Harsh Kumar asked in CO and Architecture Sep 29, 2018

303 views

0 votes

1 answer

294

Cache - No. of Index Decoders
Certainly, the DM cache will require only single Cache Index decoder, whereas the Fully - Associative Cache will not require any. My question is - How many Index decoders do we need for K-way set associative cache? Is it just one or K ?

Harsh Kumar asked in CO and Architecture Sep 28, 2018

486 views

0 votes

0 answers

295

Hierarchy or simultaneous

Deepalitrapti asked in CO and Architecture Sep 26, 2018

by Deepalitrapti

488 views

0 votes

2 answers

296

Cache memory 31

Deepalitrapti asked in CO and Architecture Sep 17, 2018

by Deepalitrapti

218 views

0 votes

0 answers

297

Deepalitrapti asked in CO and Architecture Sep 17, 2018

by Deepalitrapti

405 views

0 votes

0 answers

298

Self doubt
Main mem block number is 4,6 and 8 . Then 8 is compalsory miss or conflict miss ????

abhishekmehta4u asked in CO and Architecture Sep 16, 2018

by abhishekmehta4u

213 views

0 votes

0 answers

299

self doubt write back cache
https://gateoverflow.in/35154/write-back-and-write-through every thing is clear but a doubt is tht why only the case of dirty bit is considered ...and why the case of clean bit is left while solving ??? and when to take both cases??should be explicitly mentioned in the question??

eyeamgj asked in CO and Architecture Sep 15, 2018

161 views

0 votes

1 answer

300

Cache
What happens on write miss in a write back cache? First write in main memory then bring the block to cache (dirty bit = 0) or First bring the block to cache then write it (dirty bit = 1).

MayankSharma asked in CO and Architecture Sep 14, 2018

by MayankSharma

837 views

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Recent questions tagged cache-memory