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A Simple Illustration
Cache Memory
Recent questions tagged cache-memory
4
votes
4
answers
451
cache memory
when 8-way set associative mapping of cache memory is done and main memory size is 32 GB and Tag field has 10 bits. what will be the cache size ( consider, memory is byte addresable )
amrendra pal
asked
in
CO and Architecture
Sep 3, 2017
by
amrendra pal
3.1k
views
co-and-architecture
cache-memory
3
votes
2
answers
452
cache memory
what will be size of main memory. when 4-way set associative mapping of cache memory is done and cache size is 256 KB and Tag field has 7 bits( consider, memory is byte addresable )
amrendra pal
asked
in
CO and Architecture
Sep 3, 2017
by
amrendra pal
1.1k
views
co-and-architecture
cache-memory
1
vote
0
answers
453
[COA] Cache question with instruction mix.
Consider a CPU that executes at a clock rate of 200MHz(5ns per cycle) with a single level cache. CPI execution i.e. CPI with ideal memory is 1.1. Instruction mix are 50% arithmetic/Logical, 30% load/store, 20% control instruction. ... and we need to fetch the operand from the memory for instruction execution right ? So we need atleast 2 memory references.
Xylene
asked
in
CO and Architecture
Aug 31, 2017
by
Xylene
671
views
cache-memory
1
vote
0
answers
454
[COA] Implicit and Explicit Operands
In stack architecture do we consider the bits for A as 32 bits or 64 ? Please explain the number of bits required in stack and accumulator architecture.
Xylene
asked
in
CO and Architecture
Aug 30, 2017
by
Xylene
1.8k
views
co-and-architecture
cache-memory
1
vote
1
answer
455
COA cache question.
A computer has a cache, main memory, and a disk used for virtual memory. If a referenced word is in the cache, 20 ns are required to access it. If it is in main memory but not in the cache, 60 ns are needed to load it into the cache, and then the reference is started again. If ... 0.9(20) + 0.1( 20 + 0.6(60+20) + 0.4(60+12ms +60+20)). Please tell me whats wrong in this approach.
Xylene
asked
in
CO and Architecture
Aug 30, 2017
by
Xylene
1.3k
views
co-and-architecture
cache-memory
2
votes
1
answer
456
cache memory
Cache memory can exploit spatial locality of reference 1)by remembering which pieces of data have been accessed recently 2)when some data items are re-accessed frequently 3)by remembering which cache blocks have been recently written to 4)only if cache line size is greater than 1 byte
set2018
asked
in
CO and Architecture
Aug 29, 2017
by
set2018
541
views
co-and-architecture
cache-memory
0
votes
1
answer
457
Cache miss penalty
Suppose that in 250 memory references there are 30 misses in first level cache and 10 misses in second level cache. Assume that miss penalty from the L2cache memory are 50 cycles. The hit time of L2 cache is 10 cycles. The hit time of the L1 cache is 5 cycles. If there are 1.25 ... ;t we consider L1 hit time. Why can't the answer be 30/250(5 + (20/30)(10) + (10/30)(50+10)) ?
Xylene
asked
in
CO and Architecture
Aug 28, 2017
by
Xylene
1.2k
views
cache-memory
2
votes
2
answers
458
What is the write miss and write hit?
hem chandra joshi
asked
in
CO and Architecture
Aug 26, 2017
by
hem chandra joshi
9.4k
views
cache-memory
0
votes
1
answer
459
cache memory
"Using a faster processor chip results in a corresponding increase in performance of a computer even if the main memory speed remains the same " pls justify this statement
set2018
asked
in
CO and Architecture
Aug 23, 2017
by
set2018
1.8k
views
co-and-architecture
cache-memory
1
vote
0
answers
460
cache memory
Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache. Assume that the cache has a line size of four 32-bit words. Draw a block diagram of this cache showing its organization and how the different address fields are used ... a cache hit/miss.Where in the cache is the word from memory location ABCDE8F8 mapped? from the given info find size of word?
set2018
asked
in
CO and Architecture
Aug 23, 2017
by
set2018
559
views
co-and-architecture
cache-memory
0
votes
0
answers
461
cache memory
Let's assume a computer has a 64-byte cache block, an L2 cache that takes 7 clock cycles to get the critical 8 bytes, and then 1 clock cycle per 8 bytes + 1 extra clock cycle to fetch the rest of the block. (These parameters are similar to the ... the following instructions read data 8 bytes at a time from the rest of the block. Compare the times with and without critical word first.
set2018
asked
in
CO and Architecture
Aug 22, 2017
by
set2018
230
views
co-and-architecture
cache-memory
0
votes
1
answer
462
Cache memory
Assume that the hit time of a two-way set-associative first-level data cache is 1.1 times faster than a four-way set-associative cache of the same size. The miss rate falls from 0.049 to 0.044 for an 8 KB data cache, Assume a hit is 1 clock cycle ... the L2 cache for the two-way set-associative cache, and that the L2 cache does not miss. Which has the faster average memory access time?
set2018
asked
in
CO and Architecture
Aug 22, 2017
by
set2018
636
views
co-and-architecture
cache-memory
3
votes
2
answers
463
set associative cache
The physical address size on a machine is 36 bits.The number of tag bits in the physical address format in a 256 KB, 16 way block set associative cache is____bits. What will be the ans?
avinash41
asked
in
CO and Architecture
Aug 9, 2017
by
avinash41
778
views
cache-memory
computer
co-and-architecture
2
votes
1
answer
464
cache,memory ,secondary memory
A computer has a cache, main memory and a hard disk used for virtual memory. If referenced word is in cache, 20 ns are required to access it. If it is in main memory but not in cache 60 ns are needed to load it into cache and then ... think answer should be Cachehit * Tcache + (1-cachehit) (Tcache + Memoryhit*TMemory +( 1- Memoryhit) (TMemory+Tsec. memory ) )
Sunil8860
asked
in
CO and Architecture
Aug 8, 2017
by
Sunil8860
673
views
co-and-architecture
cache-memory
virtual-memory
effective-memory-access
9
votes
2
answers
465
wrie through updation in cache
Consider a system with cache access time 20 ns and main memory access time 140 ns. If 60% operations are read operations and hit ratio is 90%. What is the effective access time if write through updation technique is used? (a) 75.2 ns (b) 76.4 ns (c) 83.2 ns (d) 84.4 ns
Sunil8860
asked
in
CO and Architecture
Aug 6, 2017
by
Sunil8860
3.9k
views
co-and-architecture
cache-memory
write-through
2
votes
0
answers
466
CO: William Stalling: Write Through and Write Back, which is more efficient.
According to my calculation, the time required in write back is 240ns and for write through it should be 1920ns. Is it correct or not?
Shubhanshu
asked
in
CO and Architecture
Aug 5, 2017
by
Shubhanshu
797
views
co-and-architecture
cache-memory
write-through
3
votes
1
answer
467
CO: Working of multiplexer, comparator and encoder in 2-way set associative mapping
Draw the diagram which shows the mechanism of fetching the data in 2-way set associative mapping using multiplexer, comparator, and encoder?
Shubhanshu
asked
in
CO and Architecture
Aug 5, 2017
by
Shubhanshu
1.0k
views
co-and-architecture
cache-memory
multiplexer
1
vote
0
answers
468
CO: William Stalling Exercise
Figure 4.10 Figure 4.12 Figure 4.15 For a) 24, 2^16, 4 words, 2^22, 2^14, 8 b) 24, 2^16, 4 words, 2^22, 2^14, 22 And for c give your answer and verify these answer?
Shubhanshu
asked
in
CO and Architecture
Aug 5, 2017
by
Shubhanshu
305
views
co-and-architecture
cache-memory
2
votes
1
answer
469
Simultaneous Memory Organization
Please help in clearing following two points :- 1.Consider write back cache and we use simultaneous organization, as mentioned here:- https://gateoverflow.in/14480/formula-write-back-write-through-access-time-parallel-serial For simultaneous access and ... not bringing the word from main memory to cache memory then what data cache contains?How data comes to cache?
rahul sharma 5
asked
in
CO and Architecture
Jul 27, 2017
by
rahul sharma 5
1.1k
views
co-and-architecture
cache-memory
16
votes
5
answers
470
#ADDRESS INSTRUCTION
Consider the hypothetical processor is supports both 2 address and one address instructions.It has 128 word memory A 16-bit instruction is placed in the one memory word. Q1.What is the range of two address and one address instructions are supported. A)1 to ... 2-address instructions are already existed.How many one address instructions can be supported ? A)128 B)2 C)256 D)32
junaid ahmad
asked
in
CO and Architecture
Jul 24, 2017
by
junaid ahmad
16.6k
views
co-and-architecture
cache-memory
machine-instruction
instruction-format
computer-architecture
1
vote
1
answer
471
Cache Memory Made Easy
The answer in the solution is b. My confusion is that adding word to a block will reduce Miss Rate and not Miss Penalty. So shouldn't the answer be c, i.e. only S2 is correct?
kimaya
asked
in
CO and Architecture
Jul 8, 2017
by
kimaya
624
views
co-and-architecture
cache-memory
made-easy-test-series
0
votes
2
answers
472
Confusion with a term
Can someone tell me what is the actual meaning of cache access / memory access time ? Is it the time to fetch a word/byte from cache or is it the time to search the cache or is it the sum of both? If it's the time to fetch a byte then why do we add this time in hierarchical access ? It's not the searching time right?
Xylene
asked
in
CO and Architecture
Jul 6, 2017
by
Xylene
479
views
cache-memory
multilevel-cache
1
vote
2
answers
473
Cache in CO
For associative mapping, MM size = 16GB Block size = 4KB Tag bit size = 10 What will be the cache size?
Karan Patel
asked
in
CO and Architecture
Jun 25, 2017
by
Karan Patel
718
views
co-and-architecture
cache-memory
0
votes
3
answers
474
gateforum CO&A cache memory Level 2 Q17
On a system with 32 bit addresses and 4KB pages, how many levels are required in multilevel page table (assume that each entry in the page table takes 4 bytes of storage)? a. 2 b. 3 c.1 d. None of these
Satyajeet Singh
asked
in
CO and Architecture
Jun 14, 2017
by
Satyajeet Singh
463
views
co-and-architecture
cache-memory
gateforum
0
votes
2
answers
475
Gateforum Test Series: CO & Architecture - cache memory
Assume a cache of $2K$ blocks ( 1 block size = 4 words= 16 bytes) and $32-bit$ address. Assume this machine is byte addressable. What is the bit length of each field in direct mapped? $(A).\space 19,11,2$ $(B).\space 20,11,2$ $(C).\space 21,9,2$ $(D). \text{none of these}$
Satyajeet Singh
asked
in
CO and Architecture
Jun 14, 2017
by
Satyajeet Singh
1.9k
views
co-and-architecture
cache-memory
direct-mapping
gateforum
1
vote
1
answer
476
IISc PhD
If a cache memory system has only one block, which of the following options is true? It exploits both temporal and spatial locality It exploits only temporal locality but not spatial locality It exploits only spatial locality but not temporal locality It exploits neither temporal locality nor spatial locality
kauray
asked
in
CO and Architecture
Jun 9, 2017
by
kauray
564
views
iisc
iisc-interview
cache-memory
5
votes
2
answers
477
Carl-Hamacher
A computer system has a main memory consisting 1M 16 bit-words.It also has a 4K-word cache organized in the block-set-associative manner,with 4 blocks per set and 64 words per block. a)assume that the cache is initially empty.Suppose that the processor ... the improvement factor resulting from the use of the cache.Assume that LRU algorithm is used for block replacement. ans is: 2.15
reena_kandari
asked
in
CO and Architecture
Jun 7, 2017
by
reena_kandari
4.7k
views
co-and-architecture
carl-hamacher
cache-memory
2
votes
0
answers
478
Carl-Hamacher
Acomputer with a 16-bit word length has a direct-mapped cache, used for both instructions and data. Memory addresses are 16 bits long, and the memory is byte-addressable. The cache is small for illustrative purposes. It contains only four 16-bit words. ... the execution time for each pass, counting only memory access times @Arjun and @Bikram sir please have a look at this question.
reena_kandari
asked
in
CO and Architecture
Jun 7, 2017
by
reena_kandari
678
views
co-and-architecture
carl-hamacher
cache-memory
0
votes
2
answers
479
Carl hamacher
A program consists of two nested loops-a small inner loop and a much larger outer loop.The decimal memory addresses shown delineate the location of the two loops and the beginning and end of the total program. All memory locations in the various sections of ... the cycle time of the cache is 1τ s. Compute the total time needed for instruction fetching during execution of the program.
reena_kandari
asked
in
CO and Architecture
Jun 7, 2017
by
reena_kandari
1.8k
views
co-and-architecture
carl-hamacher
cache-memory
0
votes
0
answers
480
[COA[ Hamacher Problem 5.11 Find Speed up ratio
A computer system contains a main memory of 32K 16-bit words. It also has a 4Kword cache divided into four-line sets with 64 words per line. Assume that the cache is initially empty. The processor fetches words from locations ... MRU policy for block replacement. The same question with LRU has been answered:- https://gateoverflow.in/11240/cache-memory
rahul sharma 5
asked
in
CO and Architecture
May 30, 2017
by
rahul sharma 5
634
views
co-and-architecture
cache-memory
speedup
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