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3
answers
1
GATE CSE 2006 | Question: 62, ISRO2016-50
A CPU generates $32$-bit virtual addresses. The page size is $4$ KB. The processor has a translation look-aside buffer (TLB) which can hold a total of $128$ page table entries and is $4$-way set associative. The minimum size of the TLB tag is: $\text{11 bits}$ $\text{13 bits}$ $\text{15 bits}$ $\text{20 bits}$
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in
Operating System
Sep 16, 2020
25.7k
views
gatecse-2006
operating-system
virtual-memory
normal
isro2016
4
answers
2
GATE CSE 2004 | Question: 20
Which of the following addressing modes are suitable for program relocation at run time? Absolute addressing Based addressing Relative addressing Indirect addressing I and IV I and II II and III I, II and IV
answered
in
CO and Architecture
Jun 2, 2020
12.0k
views
gatecse-2004
co-and-architecture
addressing-modes
easy
9
answers
3
GATE CSE 2018 | Question: 35
Consider the following languages: $\{a^mb^nc^pd^q \mid m+p=n+q, \text{ where } m, n, p, q \geq 0 \}$ $\{a^mb^nc^pd^q \mid m=n \text{ and }p=q, \text{ where } m, n, p, q \geq 0 \}$ ... Which of the above languages are context-free? I and IV only I and II only II and III only II and IV only
comment edited
in
Theory of Computation
May 20, 2020
21.2k
views
gatecse-2018
theory-of-computation
identify-class-language
context-free-language
normal
2-marks
1
answer
4
Michael Sipser Edition 3 Exercise 2 Question 9 (Page No. 155)
Give a context-free grammar that generates the language $A=\{a^{i}b^{j}c^{k}\mid i=j$ $\text{or}$ $ j=k$ $\text{where}$ $ i,j,k\geq 0\}.$ Is your grammar ambiguous$?$ Why or why not$?$
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in
Theory of Computation
May 20, 2020
559
views
michael-sipser
theory-of-computation
context-free-language
ambiguous
grammar
6
answers
5
GATE CSE 2011 | Question: 15
The minimum number of $\text{D}$ flip-flops needed to design a mod-258 counter is 9 8 512 258
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in
Digital Logic
May 10, 2020
15.0k
views
gatecse-2011
digital-logic
normal
digital-counter
1
answer
6
GATE CSE 1994 | Question: 2-1
The number of flip-flops required to construct a binary modulo $N$ counter is __________
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in
Digital Logic
May 10, 2020
6.3k
views
gate1994
digital-logic
sequential-circuit
flip-flop
digital-counter
fill-in-the-blanks
2
answers
7
GATE CSE 2001 | Question: 11
A sequential circuit takes an input stream of $0's$ and $1's$ and produces an output stream of $0's$ and $1's.$ Initially it replicates the input on its output until two consecutive $0's$ are encountered on the input. From then ... Give the minimized sum-of-product expression for $\text{J}$ and $\text{K}$ inputs of one of its state flip-flops
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in
Digital Logic
May 10, 2020
5.3k
views
gatecse-2001
digital-logic
normal
descriptive
flip-flop
3
answers
8
TIFR CSE 2010 | Part B | Question: 21
For $x \in \{0,1\}$, let $\lnot x$ denote the negation of $x$, that is $\lnot \, x = \begin{cases}1 & \mbox{iff } x = 0\\ 0 & \mbox{iff } x = 1\end{cases}$. If $x \in \{0,1\}^n$, then $\lnot \, x$ denotes the component wise negation of $x$; that ... $g(x) = f(x) \land f(\lnot x)$ $g(x) = f(x) \lor f(\lnot x)$ $g(x) = \lnot f(\lnot x)$ None of the above.
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in
Digital Logic
May 8, 2020
3.4k
views
tifr2010
digital-logic
boolean-algebra
1
answer
9
From Geeksforgeeks
Given A, an array of size n, comprised of an increasing sequence of numbers followed immediately by a decreasing one. What is worst case time complexity of optimal algorithm to determine if a given number x is in the array?
commented
in
Algorithms
May 3, 2020
2.4k
views
algorithms
time-complexity
array
1
answer
10
Kenneth Rosen Edition 6th Exercise 1.5 Question 10 (Page No. 73)
For each of theses sets of premises, what relevant conclusions can be drawn? (b)"If I work, it is either sunny or partly sunny." "I worked last Monday or I worked Last Friday." "It was not ... only eat what tastes good." "You do not eat Tofu." "Cheeseburgers are not healthy to eat."
commented
in
Mathematical Logic
Apr 10, 2020
2.4k
views
discrete-mathematics
propositional-logic
kenneth-rosen
4
answers
11
GATE CSE 2000 | Question: 2.26
In SQL, relations can contain null values, and comparisons with null values are treated as unknown. Suppose all comparisons with a null value are treated as false. Which of the following pairs is not equivalent? $x = 5 \quad not (not (x = 5))$ $x = 5 \quad x > 4$ and $x < 6,$ where $x$ is an integer $x ≠ 5 \quad not (x = 5)$ none of the above
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in
Databases
Apr 8, 2020
18.6k
views
gatecse-2000
databases
sql
normal
13
answers
12
Minimum number of tables to represent ER-Diagram
How many minimum relations required for given ER diagram ?
commented
in
Databases
Apr 6, 2020
8.8k
views
er-diagram
databases
er-to-relational
relational
2
answers
13
ACE Academy: Recognition of CFG
$L1 =\left \{ a^{m} b^{n} c^{p} | \left ( m \geq n \right )\text{or} \left ( n = p \right ) \right \}$ $L2 =\left \{ a^{m} b^{n} c^{p} | \left ( m \geq n \right )\text{and} \left ( n = p \right ) \right \}$ $(a)$ Both are NCFL’s $(b)$ L1 is DCFL and L2 is NCFL $(c)$ L1 is NCFL and L2 is not context-free $(d)$ Both are not context-free
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in
Theory of Computation
Mar 31, 2020
800
views
context-free-grammar
context-free-language
dcfl
1
answer
14
Pc relative mode addressing
What is the intial pc value meaning 530=Pc + value what should be the pc value 631 or 632 or 633 basically the instruction length is not give so how can i determine the addr loaded in pc hen instructtion at 630 is executing because if instruction length is 4 bytes it should be 634 thanks in advance
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in
CO and Architecture
Jan 10, 2020
5.1k
views
co-and-architecture
addressing-modes
1
answer
15
unitary matrix
A is a unitary matrix. Then eigen value of A are (a) 1, – 1 (b) 1, – i (c) i, – i (d) – 1, i
comment reshown
in
Linear Algebra
Dec 2, 2019
15.3k
views
linear-algebra
matrix
eigen-value
6
answers
16
GATE CSE 2016 Set 2 | Question: 24
In an Ethernet local area network, which one of the following statements is TRUE? A station stops to sense the channel once it starts transmitting a frame. The purpose of the jamming signal is to pad the frames that are ... the packet even after the collision is detected. The exponential back off mechanism reduces the probability of collision on retransmissions.
commented
in
Computer Networks
Nov 21, 2019
11.1k
views
gatecse-2016-set2
computer-networks
ethernet
normal
6
answers
17
GATE IT 2006 | Question: 65
In the $\text{4B/5B}$ encoding scheme, every $4$ bits of data are encoded in a $5$-bit codeword. It is required that the codewords have at most $1$ leading and at most $1$ trailing zero. How many are such codewords possible? $14$ $16$ $18$ $20$
answered
in
Computer Networks
Nov 21, 2019
10.0k
views
gateit-2006
computer-networks
encoding
combinatory
normal
out-of-gate-syllabus
9
answers
18
GATE CSE 2014 Set 3 | Question: 25
Host A (on TCP/IP v4 network A) sends an IP datagram D to host B (also on TCP/IP v4 network B). Assume that no error occurred during the transmission of D. When D reaches B, which of the following IP header field(s) may be different from that of the original datagram ... $\text{ii}$ only $\text{ii}$ and $\text{iii}$ only $\text{i, ii}$ and $\text{iii}$
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in
Computer Networks
Nov 20, 2019
16.3k
views
gatecse-2014-set3
computer-networks
ip-packet
normal
19
answers
19
GATE CSE 2004 | Question: 47
Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An average instruction takes $100$ nanoseconds of CPU time, and two memory accesses. ... execution time? $\text{645 nanoseconds}$ $\text{1050 nanoseconds}$ $\text{1215 nanoseconds}$ $\text{1230 nanoseconds}$
answered
in
CO and Architecture
Nov 17, 2019
63.6k
views
gatecse-2004
co-and-architecture
virtual-memory
normal
6
answers
20
GATE CSE 2016 Set 1 | Question: 31
The size of the data count register of a $\text{DMA}$ controller is $16\;\text{bits}$. The processor needs to transfer a file of $29,154$ kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times ... needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is _________.
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in
CO and Architecture
Nov 16, 2019
18.5k
views
gatecse-2016-set1
co-and-architecture
dma
normal
numerical-answers
12
answers
21
GATE CSE 2016 Set 2 | Question: 30
Suppose the functions $F$ and $G$ can be computed in $5$ and $3$ nanoseconds by functional units $U_{F}$ and $U_{G}$, respectively. Given two instances of $U_{F}$ and two instances of $U_{G}$, it is required to implement ... $1 \leq i \leq 10$. Ignoring all other delays, the minimum time required to complete this computation is ____________ nanoseconds.
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in
CO and Architecture
Nov 16, 2019
22.7k
views
gatecse-2016-set2
co-and-architecture
data-path
normal
numerical-answers
2
answers
22
GATE CSE 1987 | Question: 1-vi
A microprogrammed control unit Is faster than a hard-wired control unit. Facilitates easy implementation of new instruction. Is useful when very small programs are to be run. Usually refers to the control unit of a microprocessor.
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in
CO and Architecture
Nov 16, 2019
7.2k
views
gate1987
co-and-architecture
control-unit
microprogramming
9
answers
23
GATE CSE 2006 | Question: 42
A CPU has a five-stage pipeline and runs at $1$ GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching new ... : $\text{1.0 second}$ $\text{1.2 seconds}$ $\text{1.4 seconds}$ $\text{1.6 seconds}$
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in
CO and Architecture
Nov 15, 2019
21.1k
views
gatecse-2006
co-and-architecture
pipelining
normal
2
answers
24
GATE CSE 2001 | Question: 12
Consider a $5-$stage pipeline - IF (Instruction Fetch), ID (Instruction Decode and register read), EX (Execute), MEM (memory), and WB (Write Back). All (memory or register) reads take place in the second phase of a clock cycle ... Show all data dependencies between the four instructions. Identify the data hazards. Can all hazards be avoided by forwarding in this case.
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in
CO and Architecture
Nov 15, 2019
17.4k
views
gatecse-2001
co-and-architecture
pipelining
normal
descriptive
6
answers
25
GATE CSE 1993 | Question: 11
In the three-level memory hierarchy shown in the following table, $p_i$ denotes the probability that an access request will refer to $M_i$ ... a page swap is $T_i$. Calculate the average time $t_A$ required for a processor to read one word from this memory system.
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in
CO and Architecture
Nov 15, 2019
11.0k
views
gate1993
co-and-architecture
cache-memory
normal
descriptive
1
answer
26
GATE CSE 2002 | Question: 10
In a C program, an array is declared as $\text{float} \ A[2048]$. Each array element is $4 \ \text{Bytes}$ in size, and the starting address of the array is $0x00000000$. This program is run on a computer that has a direct ... ? Justify your answer briefly. Assume that the data cache is initially empty and that no other data or instruction accesses are to be considered.
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in
CO and Architecture
Nov 15, 2019
6.1k
views
gatecse-2002
co-and-architecture
cache-memory
normal
descriptive
2
answers
27
GATE IT 2008 | Question: 33
Consider the following languages. $L_1 = \{a^i b^j c^k \mid i = j, k \geq 1\}$ $L_2 = \{a^i b^j \mid j = 2i, i \geq 0\}$ Which of the following is true? $L_1$ is not a CFL but $L_2$ is $L_1 \cap L_2 = \varnothing $ and $L_1$ is non-regular $L_1 \cup L_2$ is not a CFL but $L_2$ is There is a $4$-state PDA that accepts $L_1$, but there is no DPDA that accepts $L_2$.
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in
Theory of Computation
Nov 11, 2019
5.9k
views
gateit-2008
theory-of-computation
normal
identify-class-language
2
answers
28
TIFR CSE 2018 | Part B | Question: 11
Consider the language $L\subseteq \left \{ a,b,c \right \}^{*}$ defined as $L = \left \{ a^{p}b^{q}c^{r} : p=q\quad or\quad q=r \quad or\quad r=p \right \}.$ Which of the following answer is TRUE about the complexity of this language ... defined as $\overline{L} = \left \{ a,b,c \right \}^{*}\backslash L,$ is regular. $L$ is regular, context-free and decidable
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in
Theory of Computation
Nov 11, 2019
2.5k
views
tifr2018
identify-class-language
theory-of-computation
2
answers
29
TIFR CSE 2019 | Part B | Question: 10
Let the language $D$ be defined in the binary alphabet $\{0,1\}$ as follows: $D:= \{ w \in \{0,1\}^* \mid \text{ substrings 01 and 10 occur an equal number of times in w} \}$ For example , $101 \in D$ while $1010 \notin D$ ... $D$ is context-free but not regular $D$ is decidable but not context-free $D$ is decidable but not in NP $D$ is undecidable
answered
in
Theory of Computation
Nov 11, 2019
2.0k
views
tifr2019
theory-of-computation
identify-class-language
5
answers
30
GATE CSE 2002 | Question: 2.14
Which of the following is true? The complement of a recursive language is recursive The complement of a recursively enumerable language is recursively enumerable The complement of a recursive language is either recursive or recursively enumerable The complement of a context-free language is context-free
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in
Theory of Computation
Nov 11, 2019
11.4k
views
gatecse-2002
theory-of-computation
easy
closure-property
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