Digital Logic: GATE 2013 EE

Question

The clock frequency applied to the digital circuit shown in the figure below is 1 kHz. If the initial state of the output Q of the flip-flop is ‘0’, then the frequency of the output waveform Q in kHz is

• A. 0.25
• B. 0.5
• C. 1
• D. 2

Comments

B ?

initial Q=0,Q'=1 =>input to NAND gate 0,1=> X=1 so Toggle and Q=Q'=1

negative edge cycle so clock 0->1->level-> -1 ->level.......

for only falling edge Q            0->0-> 0   - >1->    1 ......

so T=2*Tc

so freq become half.[it is difficult to exp such Q without time Cycle diagram,I don't whether u got the point or not]

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What do u mean by this?

negative edge cycle so clock 0->1->level-> -1 ->level.......

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sorry its negative edge trig

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Can you provide a reference for this to clear the concept.

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you can see http://osp.mans.edu.eg/cs212/FF_Edge_Triggered.htm timing diagram.

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Can you draw the time cycle diagram and upload?

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Its mod 2 counter. So its diving the clock frequency by 2 right ?

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@Shamim Ahmed yes

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Image of Time Cycle Graph

I hope this can explain you the solution more easily.

Answer 1

From the given circuit ,X=1, so T toggles for every negative edge.

if you draw the waveform , clock will get doubled. so frequencey will gets reduce to half.

therefore the answer for this problem becomes 0.5KHz,