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Recent questions tagged adder

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0 answers

31

Self Doubt
Suppose we are using 4-bit carry lookahead adder modules to build a 64- bit adder with two-level carry lookahead, with ripple carry between the modules. If the delay of a basic gate (AND, OR, NOT) is 2 nanoseconds, the worst-case delay of the 64-bit adder will be ……….. nanoseconds.

jatin khachane 1 asked in Digital Logic Nov 7, 2018

by jatin khachane 1

957 views

1 vote

2 answers

32

Gateforum Test Series: Digital Logic - Adder

Gupta731 asked in Digital Logic Nov 6, 2018

607 views

0 votes

2 answers

33

Na462 asked in Digital Logic Oct 1, 2018

by Na462

838 views

2 votes

2 answers

34

Sums on Adder
$1)$3-bit ripple adder, which adds two 3-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, ... both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder?

srestha asked in Digital Logic Aug 30, 2018

3.2k views

1 vote

1 answer

35

Adder delay
A full adder circuit takes 20 ns to generate the carry-out bit and 40 ns for the sum bit. When 4, 1 bit full adders are cascaded, the maximum rate of additions per second will be $\text{____} \times 10^6 $sec. Usual Solution given The ... calculate the total time taken to perform one round of four bit addition. Right? (Similar old question: https://gateoverflow.in/83500/digitals)

GateAspirant999 asked in Digital Logic Aug 19, 2018

by GateAspirant999

4.4k views

0 votes

0 answers

36

Doubt
How to check whether there is overflow in n-bit parallel adder?

aditi19 asked in Digital Logic Aug 3, 2018

460 views

0 votes

1 answer

37

gate 2004
A $4 \hspace{0.1cm} bit$ carry lookahead adder which add two $4$ $bit$ number is designed using $AND ,OR,NOT,NAND,NOR$ gates only.Assuming that all the inputs are available in both complemented and uncomplemented form and the delay of each gate is one time ... is if we take same $4$ $bit$ number instead of lookahead adder if we take parallel adder what will be overall propagation delay??

BASANT KUMAR asked in Digital Logic May 27, 2018

by BASANT KUMAR

963 views

0 votes

1 answer

38

Adder
One ripple carry adder is adding two n-bit integers. The time complexity to perform addition using this adder is (We know carry look ahead adder takes time log n. Is it similar for other adders too). Plz also share some good resource about these two adders

srestha asked in Digital Logic May 21, 2018

1.3k views

2 votes

0 answers

39

Digital Logic
Please elaborate your answer.

gauravkc asked in Digital Logic Jan 9, 2018

552 views

1 vote

1 answer

40

CLA and RCA delays.
How to analyse the delays of Ripple carry adder and Carry look ahead adder. Please explain with Example.

AnilGoudar asked in Digital Logic Dec 30, 2017

567 views

1 vote

0 answers

41

Parshu gate asked in Digital Logic Dec 5, 2017

657 views

0 votes

3 answers

42

MadeEasy Test Series: Digital Logic - Adder
A 1-bit full adder circuit takes 5 ns to generate the carry-out bit and 10 ns for the sum-bit. When 4, 1-bit full adders are cascaded, the maximum rate of additions per second will be _______ × 107.

shivangi5 asked in Digital Logic Dec 4, 2017

1.4k views

0 votes

1 answer

43

MadeEasy Test Series: Digital Logic - Adder

Jaspreet Kaur Bains asked in Digital Logic Dec 3, 2017

by Jaspreet Kaur Bains

552 views

5 votes

0 answers

44

Modified GATE 2003 question
Consider this GATE 2003 question: https://gateoverflow.in/937/gate2003-46 Here, instead of XOR gates we had OR gates, then which of the following operations can we perform? $A + B, A - B\ and\ A + 1$

Rishabh Gupta 2 asked in CO and Architecture Nov 3, 2017

by Rishabh Gupta 2

1.2k views

0 votes

1 answer

45

MadeEasy WorkBook: Digital Logic - Adder

charul asked in Digital Logic Oct 27, 2017

by charul

622 views

2 votes

1 answer

46

Digital Systems - Help building a 4 bit Binary adder circuit

Garrett McClure asked in Digital Logic Oct 1, 2017

by Garrett McClure

1.8k views

1 vote

0 answers

47

made easy book
If the carry propogation delay is 5 in full adder then multiplication of 8 bit number using co-multiplier takes(Assume AND gate delay=2)

nikkey123 asked in Digital Logic Sep 16, 2017

352 views

1 vote

2 answers

48

Which expression is right with respect to carry look header?
(i) Ci +1= Gi+ PiCi (ii) Ci +1= G(i+1) + P(i+1)Ci https://www.youtube.com/watch?v=9lyqSVKbyz8&index=116&list=PLBlnK6fEyqRjMH3mWf6kwqiTbT798eAOm i or ii ?

hem chandra joshi asked in Digital Logic Sep 7, 2017

by hem chandra joshi

461 views

0 votes

1 answer

49

adder
This is binary to radix -12 circuit, how?

Sunil8860 asked in Digital Logic Aug 30, 2017

661 views

9 votes

4 answers

50

ISRO2017-24
When two $n$-bit binary numbers are added the sum will contain at the most $n$ bits $n + 2$ bits $n + 3$ bits $n + 1$ bits

sh!va asked in Digital Logic May 7, 2017

by sh!va

7.7k views

0 votes

1 answer

51

ISRO 2007-ECE Half Adder Circuit
A half adder can be constructed using two $2$-input logic gates. One of them is an $\text{AND}$-gate, the other is $\text{OR}$ $\text{NAND}$ $\text{NOR}$ $\text{EX-OR}$

sh!va asked in Digital Logic Mar 2, 2017

by sh!va

716 views

1 vote

1 answer

52

ISRO2016-ECE Digital Logic
How many inputs & outputs does a full adder have? $3, 2$ $2, 3$ $3, 3$ $2, 2$

sh!va asked in Digital Logic Feb 21, 2017

by sh!va

527 views

3 votes

1 answer

53

Test by Bikram | Mock GATE | Test 3 | Question: 24
A $4-bit$ carry-lookahead adder adds two $4-bit$ numbers. The adder is designed only using $AND, OR, NOT, NAND $ and $NOR$ gates. We assume that all the inputs are available in both complemented and uncompleted forms. The delay ... using two-level $AND-OR$ logic. Thus, the overall propagation delay of the adder is ______ in terms of time units.

Bikram asked in GATE Feb 9, 2017

by Bikram

588 views

1 vote

1 answer

54

vaishali jhalani asked in Digital Logic Jan 4, 2017

by vaishali jhalani

910 views

7 votes

2 answers

55

GATE CSE 1988 | Question: 4ii
Using binary full adders and other logic gates (if necessary), design an adder for adding $4$-bit number (including sign) in $2’s$ complement notation.

go_editor asked in Digital Logic Dec 19, 2016

3.0k views

0 votes

0 answers

56

full adder
Can anyone explain me this theory with an example(from the third line)...??

Anmol Verma asked in Digital Logic Dec 14, 2016

811 views

0 votes

1 answer

57

Virtual Gate Test Series: Digital Logic - Ripple Carry Adder
Which of the following statements is/are true? S1: Carry-lookahead adder is faster compared to a ripple carry adder. S2: The cost is higher for a carry lookahead adder compared to a ripple carry adder. S1 only S2 only Both None of these

Tendua asked in Digital Logic Dec 8, 2016

by Tendua

961 views

1 vote

1 answer

58

Test by Bikram | Digital Logic | Test 2 | Question: 13
Which of the following combinations is sufficient to build a half adder? EX-OR gate and NOR gate. EX-OR gate and OR gate. EX-OR gate and AND gate. Four NAND gates.

Bikram asked in Digital Logic Nov 26, 2016

by Bikram

221 views

34 votes

1 answer

59

GATE CSE 1990 | Question: 1-i
Fill in the blanks: In the two bit full-adder/subtractor unit shown in below figure, when the switch is in position $2$ ___________ using _________ arithmetic.

makhdoom ghaya asked in Digital Logic Nov 18, 2016

by makhdoom ghaya

6.5k views

1 vote

0 answers

60

GATE CSE 1987 | Question: 3a
Design an $8 \times 8$ multiplier using five $4$-bits adders and $4$ ROM's each programmed to realise $4 \times 4$ multiplier.

makhdoom ghaya asked in Digital Logic Nov 11, 2016

by makhdoom ghaya

653 views

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Recent questions tagged adder