Login
Register
@
Dark Mode
Profile
Edit my Profile
Messages
My favorites
Register
Activity
Q&A
Questions
Unanswered
Tags
Subjects
Users
Ask
Previous Years
Blogs
New Blog
Exams
Dark Mode
Recent questions tagged carry-generator
3
votes
3
answers
1
NIELIT 2016 MAR Scientist B - Section C: 2
In which of the following adder circuits, the carry look ripple delay is eliminated? Half adder Full adder Parallel adder Carry-look ahead adder
admin
asked
in
Digital Logic
Mar 31, 2020
by
admin
3.9k
views
nielit2016mar-scientistb
digital-logic
combinational-circuit
adder
carry-generator
0
votes
0
answers
2
Morris Mano Edition 3 Exercise 5 Question 6 (Page No. 198)
(a) Redefine the carry propagate and carry generate as follows: $P _i = A _i + B _ i$ $G _i = A _iB _i$ ... circuit for this IC. [Hint: use the equation substitution method and AND-OR-INVERT funtion given in part (a) for $C _{i+1}$
ajaysoni1924
asked
in
Digital Logic
Apr 3, 2019
by
ajaysoni1924
1.0k
views
digital-logic
morris-mano
combinational-circuit
adder
carry-generator
0
votes
0
answers
3
Morris Mano Edition 3 Exercise 5 Question 5 (Page No. 198)
Using the AND-OR-Invert implementation procedure, show that the output carry in full adder can be expressed as $C _{i+1} = G _i + P _iC _i = (G _i'P _i + G _i'C _i')'$ IC type 74182 is a look-ahead carry generator MSI ... $C _1'$).
ajaysoni1924
asked
in
Digital Logic
Apr 3, 2019
by
ajaysoni1924
485
views
digital-logic
morris-mano
combinational-circuit
adder
carry-generator
1
vote
3
answers
4
Full adder
Na462
asked
in
Digital Logic
Nov 15, 2018
by
Na462
946
views
digital-logic
carry-generator
adder
full-adder
0
votes
0
answers
5
Ripple carry adder
Refer : https://gateoverflow.in/8250/gate2015-2-48 Here i dont understood how they calculated 12ns . I got that the first full adder will take 4.8ns time at that 4.8 ns we'll get the carry as well as the sum, in that duration the first XOR Ai ... for subsequent operands but for final sum the carry first need to be propagated through all full adder first Why 4.8 + 3*2.4 ??
Na462
asked
in
Digital Logic
Nov 13, 2018
by
Na462
415
views
digital-logic
carry-generator
1
vote
0
answers
6
Full Adder
The Cout function of a 3-bit adder is as follows: AB + Cin (A ⊕ B) ----- i It, being a majority function, can also be written as: AB+BCin+CinA which is equivalent to AB + Cin (A+B) ------- ii So, if we consider eqn i and ii, doesn't it show that (A ⊕ B) = (A+B). What am I missing here?
superak96
asked
in
Digital Logic
Oct 18, 2018
by
superak96
601
views
full-adder
digital-logic
carry-generator
digital-circuits
majority-circuit
0
votes
2
answers
7
Full adder
Na462
asked
in
Digital Logic
Oct 1, 2018
by
Na462
826
views
digital-logic
adder
carry-generator
0
votes
1
answer
8
Adder
One ripple carry adder is adding two n-bit integers. The time complexity to perform addition using this adder is (We know carry look ahead adder takes time log n. Is it similar for other adders too). Plz also share some good resource about these two adders
srestha
asked
in
Digital Logic
May 21, 2018
by
srestha
1.3k
views
digital-logic
carry-generator
adder
1
vote
1
answer
9
CLA and RCA delays.
How to analyse the delays of Ripple carry adder and Carry look ahead adder. Please explain with Example.
AnilGoudar
asked
in
Digital Logic
Dec 30, 2017
by
AnilGoudar
564
views
digital-logic
carry-generator
adder
1
vote
2
answers
10
Carry lookahead adder
can anyone tell me wat is the right equation for carry generator in carry lookahead adder ?? Confused .. $ C_{i} = G_{i}+P_{i}C_{i-1}$ $ C_{i+1}=G_{}i+P_{}iC_{}i$
Puja Mishra
asked
in
Digital Logic
Dec 18, 2017
by
Puja Mishra
728
views
digital-logic
look-ahead-adder
carry-generator
0
votes
0
answers
11
Ripple Carry Adder
Q.A one bit full adder takes 75 nsec to produce sum and 50 nsec to produce carry.A 4 bit parallel adder is designed using this type of full adder. The maximum rate of additions per second can be provided by 4 bit parallel adder......?
junaid ahmad
asked
in
Digital Logic
Dec 8, 2017
by
junaid ahmad
704
views
digital-logic
carry-generator
2
votes
0
answers
12
Doubt on overflow condition in case of carry propagated
The condition for overflow in the addition of two 2's complement numbers in terms of the carry propagated by the two most significant bits is ___________.
Tuhin Dutta
asked
in
Digital Logic
Nov 3, 2017
by
Tuhin Dutta
524
views
digital-logic
carry-generator
1
vote
2
answers
13
Count the no of various Gates required in Carry Generator and look ahead adder
Count the 2 Input And, OR and EX-OR gates required in Carry Generator and Look ahead adder. Note :- In the question it is asking about 2 input, not multiple input, for Multiple input AND gates in n bit carry generator we require (n(n+1))/2 and OR Gates n.
Shubhanshu
asked
in
Digital Logic
Sep 30, 2017
by
Shubhanshu
1.2k
views
digital-logic
carry-generator
look-ahead-adder
1
vote
2
answers
14
Which expression is right with respect to carry look header?
(i) Ci +1= Gi+ PiCi (ii) Ci +1= G(i+1) + P(i+1)Ci https://www.youtube.com/watch?v=9lyqSVKbyz8&index=116&list=PLBlnK6fEyqRjMH3mWf6kwqiTbT798eAOm i or ii ?
hem chandra joshi
asked
in
Digital Logic
Sep 7, 2017
by
hem chandra joshi
451
views
adder
carry-generator
2
votes
2
answers
15
MadeEasy Test Series: Digital Logic - Carry Generator
The number of AND gates are present inside a 5-bit carry look ahead generator circuit are ______.
Sandeep Singh
asked
in
Digital Logic
Jan 13, 2016
by
Sandeep Singh
1.2k
views
digital-logic
carry-generator
made-easy-test-series
70
votes
6
answers
16
GATE CSE 2006 | Question: 36
Given two three bit numbers $a_{2}a_{1}a_{0}$ and $b_{2}b_{1}b_{0}$ and $c$ ...
Rucha Shelke
asked
in
Digital Logic
Sep 22, 2014
by
Rucha Shelke
15.0k
views
gatecse-2006
digital-logic
normal
carry-generator
adder
57
votes
3
answers
17
GATE CSE 2007 | Question: 35
In a look-ahead carry generator, the carry generate function $G_i$ and the carry propagate function $P_i$ for inputs $A_i$ and $B_i$ are given by: $P_i = A_i \oplus B_i \text{ and }G_i = A_iB_i$ The expressions for the sum bit $S_i$ and the carry bit $C_{i+1}$ of ... with $S_3, S_2, S_1, S_0$ and $C_4$ as its outputs are respectively: $6, 3$ $10, 4$ $6, 4$ $10, 5$
Kathleen
asked
in
Digital Logic
Sep 21, 2014
by
Kathleen
12.8k
views
gatecse-2007
digital-logic
normal
carry-generator
adder
To see more, click for the
full list of questions
or
popular tags
.
Subscribe to GATE CSE 2024 Test Series
Subscribe to GO Classes for GATE CSE 2024
Quick search syntax
tags
tag:apple
author
user:martin
title
title:apple
content
content:apple
exclude
-tag:apple
force match
+apple
views
views:100
score
score:10
answers
answers:2
is accepted
isaccepted:true
is closed
isclosed:true
Recent Posts
Post GATE 2024 Guidance [Counseling tips and resources]
GATE CSE 2024 Result Responses
[Project Contest] Pytorch backend support for MLCommons Cpp Inference implementation
Participating in MLCommons Inference v4.0 submission (deadline is February 23 12pm IST)
IIITH PGEE 2024 Test Series by GO Classes
Subjects
All categories
General Aptitude
(3.5k)
Engineering Mathematics
(10.4k)
Digital Logic
(3.6k)
Programming and DS
(6.2k)
Algorithms
(4.8k)
Theory of Computation
(6.9k)
Compiler Design
(2.5k)
Operating System
(5.2k)
Databases
(4.8k)
CO and Architecture
(4.0k)
Computer Networks
(4.9k)
Artificial Intelligence
(79)
Machine Learning
(48)
Data Mining and Warehousing
(25)
Non GATE
(1.4k)
Others
(2.7k)
Admissions
(684)
Exam Queries
(1.6k)
Tier 1 Placement Questions
(17)
Job Queries
(80)
Projects
(11)
Unknown Category
(870)
64.3k
questions
77.9k
answers
244k
comments
80.0k
users
Recent questions tagged carry-generator
Recent Blog Comments
category ?
Hi @Arjun sir, I have obtained a score of 591 in ...
download here
Can you please tell about IIT-H mtech CSE self...
Please add your admission queries here:...