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Recent questions tagged memory-interfacing
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31
Please explain this concept.
Markzuck
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in
CO and Architecture
Oct 26, 2018
by
Markzuck
201
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co-and-architecture
memory-interfacing
test-series
1
vote
0
answers
32
Design and simulate a 1m*16 memory module using 512k*8 SRAM and perform read and write operation
I have a projecp to submit please help me to design and simulate a 1m * 16 memory module using 512k * 8 SRAM and perform read and write operations for the above memory
Arati rotti
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in
CO and Architecture
Oct 23, 2018
by
Arati rotti
900
views
co-and-architecture
memory-interfacing
0
votes
0
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33
ace test series
can anyone explain all 3 ?
newdreamz a1-z0
asked
in
CO and Architecture
Oct 21, 2018
by
newdreamz a1-z0
292
views
co-and-architecture
memory-interfacing
bus-configuration
ace-test-series
0
votes
1
answer
34
ROM system
How many address and data lines in 1M×16 ROM system
Abikkkaaa
asked
in
CO and Architecture
Oct 2, 2018
by
Abikkkaaa
371
views
co-and-architecture
rom
memory-interfacing
numerical-answers
0
votes
1
answer
35
Assignment
How many 512×8 RAM chips are needed to provide a memory capacity of 2048 bytes
Harrydszouza
asked
in
CO and Architecture
Sep 17, 2018
by
Harrydszouza
384
views
co-and-architecture
memory-interfacing
numerical-answers
0
votes
0
answers
36
CO general doubt
Consider an array has 100 elements and each element occupies 4 words .A 32 word cache is used and divided into a block of 8 words .What is the hit ratio for this statement for(i=0; i<100; i++) A[i] = A[i]+10; I just want to ask that whenever ... ie 2 elements) are fetched and placed in cache,so why we are doing like this is it because we have to follow law of spatial locality ?
Prince Sindhiya
asked
in
CO and Architecture
Sep 14, 2018
by
Prince Sindhiya
392
views
co-and-architecture
memory-interfacing
array
cache-memory
general-topic-doubt
2
votes
1
answer
37
Memory interfacing
A memory constructed with 2B words and capacity of memory $2^{18}$ bits. Number of decoder required and type of decoder if memory built using $1K\times 4$ RAM chips? (if possible give some reference and diagram)
srestha
asked
in
CO and Architecture
Mar 24, 2018
by
srestha
1.1k
views
co-and-architecture
memory-interfacing
memory-management
46
votes
3
answers
38
GATE CSE 2018 | Question: 23
A $32\text{-bit}$ wide main memory unit with a capacity of $1\;\textsf{GB}$ is built using $256\textsf{M} \times 4\text{-bit}$ DRAM chips. The number of rows of memory cells in the DRAM chip is $2^{14}$. The ... The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is _________.
gatecse
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in
CO and Architecture
Feb 14, 2018
by
gatecse
25.7k
views
gatecse-2018
co-and-architecture
memory-interfacing
normal
numerical-answers
1-mark
2
votes
1
answer
39
Computer organisation
I know that correct answer is none of these But I need explanation with answer
Harikesh Kumar
asked
in
CO and Architecture
Jan 14, 2018
by
Harikesh Kumar
418
views
co-and-architecture
memory-interfacing
memory
3
votes
3
answers
40
Hardware requirement in 16-way Set Associative Cache
Cache size 32 KB Block size = 32 Bytes Address size = 28 bit. Associativity of Cache = 16 Determine what is the hardware requirement to design the 16-way set associative cache. Hardware requirement -> Mux, Comparator, Demux, Decoder, Encoder ... lines are 5. 4) 64 And gates 5) 1 OR gate input line = 64 Someone, please verify these attributes??
Shubhanshu
asked
in
CO and Architecture
Nov 6, 2017
by
Shubhanshu
3.1k
views
cache-memory
co-and-architecture
multiplexer
memory-interfacing
0
votes
1
answer
41
Memory Interfacing problem in Computer Organisation and Architecture
Hi All, I have one doubt regarding avg access time in various levels of memory. There are 2 ways in which the processor is connected to various levels of memory. 2 levels Case 1: (parallel access) T avg = H1 * T1 + ( ... , nothing is mentioned solved via case 1 only. Can anyone please let me know which one should I use. Thank you.
souravsaha
asked
in
CO and Architecture
Oct 14, 2017
by
souravsaha
1.0k
views
co-and-architecture
memory-interfacing
2
votes
1
answer
42
Size of Tag directory
Consider a machine with 4way set associative data cache of size 32 Kbytes and block size 8 byte. The cache is managed using 32 bit virtual addressed and page size is 5 Kbytes. What is the total size of the tags in the cache directory is _________ (in K bits). Given answer is 76 I am getting 19.
Shubhanshu
asked
in
CO and Architecture
Sep 27, 2017
by
Shubhanshu
6.1k
views
co-and-architecture
cache-memory
memory-interfacing
0
votes
1
answer
43
hamacher
A disk has 24 recording surfaces ,it has a total of 14,000 cylinders.there is an average of 400 sectors per track.Each sector contain 512 bytes of data a) using a 32 bit word suggest a suitable scheme for specifying the disk address.Assuming that there are 512 bytes per sector
set2018
asked
in
CO and Architecture
Aug 26, 2017
by
set2018
409
views
co-and-architecture
carl-hamacher
disk
memory-interfacing
1
vote
1
answer
44
16bit vs 32bit vs 64bit Memory interfacing
In 16 bit processor like 8086, we have the concept of big Endian and small Endian which is related to even and odd bank of memory used in memory address interpretation. For 32 bit and 64 bit, such mechanism exist or not?
Shubhanshu
asked
in
CO and Architecture
Aug 2, 2017
by
Shubhanshu
424
views
co-and-architecture
memory-interfacing
0
votes
0
answers
45
[COA] Cache Set associative mapping
Question 1:- Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache. Assume that the cache has a line size of four 32-bit words. Draw a block diagram of this cache showing its organization and how the different ... of bits taken were 6 ? How can i identify whether we need to convert to byte addressable from word size or not?
rahul sharma 5
asked
in
CO and Architecture
May 24, 2017
by
rahul sharma 5
1.1k
views
co-and-architecture
cache-memory
memory-interfacing
0
votes
3
answers
46
[COA][ Hamacher 1.6] Cache memory
1.6 Suppose that execution time for a program is directly proportional to instruction access time and that access to an instruction in the cache is 20 times faster than access to an instruction in the main memory. Assume that a requested instruction ... added only one then please explain why? part B) Does doubling cache means access time of cache is also doubled?
rahul sharma 5
asked
in
CO and Architecture
May 22, 2017
by
rahul sharma 5
1.8k
views
co-and-architecture
memory-interfacing
cache-memory
12
votes
2
answers
47
ISRO2017-18
How many $128\times 8$ bit RAMs are required to design $32\;\text{K}\times 32$ bit RAM? $512$ $1024$ $128$ $32$
sh!va
asked
in
CO and Architecture
May 7, 2017
by
sh!va
7.1k
views
isro2017
co-and-architecture
memory-interfacing
1
vote
0
answers
48
ISRO2013-ECE Computer architecture
A memory system of size $16 \;\text{K}$ bytes is required to be designed using memory chips which have $12$ address lines and $4$ data lines each. The number of such chips required to design the system is: $2$ $4$ $8$ $16$
sh!va
asked
in
CO and Architecture
Feb 27, 2017
by
sh!va
482
views
isro-ece
isro2013-ece
co-and-architecture
memory-interfacing
3
votes
0
answers
49
Cache memory
Cache is having 80% hit ratio only for read operations. Suppose cache access require 20 cycles and main memory require 120 cycles. If there is a cache miss and the data is first transferred to the cache from main memory then cpu access it from cache. If ... be the hit ratio when both read and write are considered? Assume write through technique is used. What is the average access time?
Hardik Vagadia
asked
in
CO and Architecture
Jan 14, 2017
by
Hardik Vagadia
1.5k
views
cache-memory
co-and-architecture
memory-interfacing
0
votes
3
answers
50
Cache memory
Is it compulsory that the block sizes of the main memory and the cache memory are always equal?
Hardik Vagadia
asked
in
CO and Architecture
Jan 9, 2017
by
Hardik Vagadia
1.0k
views
cache-memory
co-and-architecture
memory-interfacing
1
vote
0
answers
51
test series question
Consider a system with CPI of 1.0 on a 5 GHz machine with a 2% miss rate and memory access time of 100ns. To reduce miss penalty designers decided to add a L2 cache with 5ns access time and decrease of overall main memory miss rate to 0.5%, How ... access - Adding a L2 cache with 5ns access time and decrease of overall main memory miss rate to 0.5%, what miss penalty reduced?
Rajesh Raj
asked
in
CO and Architecture
Dec 25, 2016
by
Rajesh Raj
758
views
test-series
co-and-architecture
memory-interfacing
normal
1
vote
0
answers
52
ravula test
Consider a computer system in which cache memory write hit takes 10ns and and miss takes 100ns. Cache memory read hit takes 5ns and miss takes 55ns. The cache is having 90% hit. The system received 1000 fetch instructions out of which, 500 operand fetch operations and 500 operand write operations. The average time taken to execute above 1000 instructions is___________?
Rajesh Raj
asked
in
CO and Architecture
Dec 25, 2016
by
Rajesh Raj
1.0k
views
test-series
co-and-architecture
memory-interfacing
bad-question
4
votes
2
answers
53
coa morris mano numerical cache memory gate also important
A digital computer has a memory unit of 64K x 16 and a cache memory of 1K words. The cache uses direct mapping with a block size of 4 words. a. How many bits are there in the tag, index, block and word fields of ... of the cache, and how are they divided into functions? Include the valid bit. c. How many blocks can the cache accommodate?
LavTheRawkstar
asked
in
CO and Architecture
Nov 26, 2016
by
LavTheRawkstar
15.8k
views
co-and-architecture
memory-interfacing
1
vote
2
answers
54
memory numerical coa
The content of PC in the basic computer is 3AF (all numbers are in hexadecimal). The content of AC is 7EC3. The content of memory at address 3AF is 932E. The content of memory at address 32E is 09AC. The content of memory at address 9AC is 8B9F. a. ... AC, and IR in hexadecimal and the values of E, I, and the sequence counter SC in binary at the end of the instruction cycle.
LavTheRawkstar
asked
in
CO and Architecture
Nov 26, 2016
by
LavTheRawkstar
8.3k
views
co-and-architecture
memory-interfacing
4
votes
0
answers
55
GATE CSE 1990 | Question: 4-iv
State whether the following statements are TRUE or FALSE with reason: Transferring data in blocks from the main memory to the cache memory enables an interleaved main memory unit to operate at its maximum speed.
makhdoom ghaya
asked
in
CO and Architecture
Nov 23, 2016
by
makhdoom ghaya
2.8k
views
gate1990
true-false
co-and-architecture
cache-memory
memory-interfacing
3
votes
2
answers
56
No. of Tag bits in Set Associative cache memory.
Consider the memory system in which the block size in cache and main memory are equal. Cache consists of 512 blocks and main memory consists of 8192 blocks. Cache is 4-way set associative ,calculate the number of tag bits in cache?
biranchi
asked
in
CO and Architecture
Nov 16, 2016
by
biranchi
4.8k
views
co-and-architecture
cache-memory
memory-interfacing
0
votes
0
answers
57
computer organization (co)
Why different clock cycle is needed for sending address and control signal . why not in one cycle?
Rajat Agarwal 1
asked
in
CO and Architecture
Nov 10, 2016
by
Rajat Agarwal 1
261
views
co-and-architecture
memory-interfacing
–1
vote
1
answer
58
Gate Application COA Morris Mano [ Numerical on Addressing Modes]
An instruction is stored at location 300 with its address fields at location 301. The address field has the value 400. A processor register RI contain the number 200. Evaluate the effective address if the addressing mode of the ... Direct (b) Immediate (c) Relative (d) Register Indirect (e) Index with RI as the Index register.
LavTheRawkstar
asked
in
CO and Architecture
Nov 4, 2016
by
LavTheRawkstar
9.9k
views
co-and-architecture
digital-logic
memory-interfacing
computer
3
votes
2
answers
59
Morris Mano Numerical
How many 128 × 8 RAM chips are needed to provide a memory capacity of 2048 bytes? How many lines of the address bus must be used to access 2048 byte of memory? How many of these lines will be common to all chips? How many lines must be decoded for chip select? Specify the size of the decoders?
LavTheRawkstar
asked
in
CO and Architecture
Nov 3, 2016
by
LavTheRawkstar
34.7k
views
co-and-architecture
digital-logic
memory-interfacing
2
votes
1
answer
60
Morris Mano Numerical Chapter 12 Question 5
A computer employs RAM chips of 256 $\times$ 8 and ROM chips of 1024 $\times$ 8. The computer system needs 2K bytes of RAM, 4K bytes of ROM and four interface units, each with four registers. A memory-mapped I/O configuration is ... for the system. Give the address ranges in hex for RAM, ROM and interface. Show the interconnection of CPU and the chips.
LavTheRawkstar
asked
in
CO and Architecture
Nov 3, 2016
by
LavTheRawkstar
12.1k
views
co-and-architecture
digital-logic
memory-interfacing
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