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A variation on Digital Logic: Morris Mano Edition 3 Exercise 7 Question 4 (Page No. 303)
Design a counter according to the state diagram above using only NAND gates and JK Flip-flops (if needed) complete with state tables

Redcom1988 asked in Digital Logic Dec 23, 2023

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MORRIS MANO BOOK
ANALYZE THE CIRCUIT GIVEN ABOVE.

anandi753951 asked in Digital Logic Nov 16, 2023

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3

Digital Logic Design
What is the correct answer of this Question ?

Sandeep652025 asked in Digital Logic Sep 20, 2023

by Sandeep652025

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4

MorrisMano 2017 Ex 2.6 d)
Reduce the following Boolean expression to the required number of literals (A+C+D)(A+C+D')(A+C+D)(A+B')

Priyankalora asked in Digital Logic Jul 31, 2023

by Priyankalora

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5

Digital logic and computer design Morris Mano 2017 Exercise 2.7 pg no 62
Find the complement of the following Boolean functions and reduce them to a minimum number of literals a) (BC'+A'D)(AB'+CD') b)B'D+A'BC'+ACD+A'BC c)[(AB)'A][(AB)'B] d)AB'+C'D'

Priyankalora asked in Digital Logic Jul 30, 2023

by Priyankalora

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Morris Mano Ex 2.6 Edition 2017
Reduce the following Boolean expressions to the required number of literals. (a) ABC+A'B'C+A'BC+ABC+A'B'C to five literals (b) BC+AC'+AB+ BCD to four literals (c) [ (CD)' + A ]' +A+CD+ AB to three literals (d) (A + C + D)(A + C + D')(A + C + D)(A + B') to four literals

Priyankalora asked in Digital Logic Jul 30, 2023

by Priyankalora

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Morris Mano Edition 3 Exercise 9 Question 24 (Page No. 396)
The boolean functions for the input of SR latch are as follows. Obtain the circuit diagram using a minimum number of NAND gates. $S = x _1’x _2’x _3 + x _1x _2x _3$. $R = x _1x _2’ + x _2x _3’$

ajaysoni1924 asked in Digital Logic Apr 8, 2019

by ajaysoni1924

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Morris Mano Edition 3 Exercise 9 Question 23 (Page No. 396)
Draw the logic diagram of the product of sum expression $ Y = (x _1 + x _2’)(x _2 + x _3)$ Show that there is a static 0 hazard when $x _1$ and $x _3$ is equal to zero and $x _2$ goes from 0 to 1.Find a way to remove hazard by adding one more OR gate.

ajaysoni1924 asked in Digital Logic Apr 8, 2019

by ajaysoni1924

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Morris Mano Edition 3 Exercise 9 Question 22 (Page No. 396)
Find a circuit that has no static hazard and implements the boolean function: F(A,B,C,D) = $\sum(0,2,6,7,8,10,12)$

ajaysoni1924 asked in Digital Logic Apr 8, 2019

by ajaysoni1924

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Morris Mano Edition 3 Exercise 9 Question 18 (Page No. 395)
Merge each of the primitive flow table shown in the figure. Proceed as follows: Find all compatible pairs by means of implication table. Find the maximal compatibles by means of a merger diagram FInd the minimal set of compatibles that covers all the states and is closed.

ajaysoni1924 asked in Digital Logic Apr 8, 2019

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Morris Mano Edition 3 Exercise 9 Question 17 (Page No. 395)
Reduce the number of states in the state table listed below. Use an implication table.

ajaysoni1924 asked in Digital Logic Apr 8, 2019

by ajaysoni1924

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Morris Mano Edition 3 Exercise 9 Question 16 (Page No. 395)
Using the implication table method, show that the state table listed in the figure cannot be reduced any further.

ajaysoni1924 asked in Digital Logic Apr 8, 2019

by ajaysoni1924

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13

Morris Mano Edition 3 Exercise 9 Question 15 (Page No. 395)
Assign output values to the don’t care states in the flow tables in the figure below in such a way as to avoid transient output places

ajaysoni1924 asked in Digital Logic Apr 8, 2019

by ajaysoni1924

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14

Morris Mano Edition 3 Exercise 9 Question 14 (Page No. 394)
It is necessary to design an asynchronous sequential circuit with two inputs, $x _1 and x _2$, and one output $z$. Initially, both input and output are zero. when $x _1 and x _2$ becomes 1, z becomes 1. when the ... for the circuit and show that it can be reduced to the flow table shown in the figure complete the design of the circuit.

ajaysoni1924 asked in Digital Logic Apr 8, 2019

by ajaysoni1924

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15

Morris Mano Edition 3 Exercise 9 Question 13,25 (Page No. 394)
A traffic light is installed at the junction of the railroad and a road. The traffic light is controlled by two switches in the rails placed one mile apart on either side of the junction. A switch is turned on when a ... circuit. show that the flow table can be reduced to four rows Complete the circuit specified in the above problem.

ajaysoni1924 asked in Digital Logic Apr 8, 2019

by ajaysoni1924

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16

Morris Mano Edition 3 Exercise 9 Question 12 (Page No. 394)
Obtain a primitive flow table for a circuit with two inputs, $x _1 and x _2$ and two outputs $y _1 and y _2$, that satisfy the following four conditions. When $x _1x _2 = 00$, the output is $z _1z _2 = 00$. when $x _1 = 1$ and ... $x _1$ changes from 0 to 1, the output is $z _1z _2$ = 10. otherwise the output does not change.

ajaysoni1924 asked in Digital Logic Apr 8, 2019

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17

Morris Mano Edition 3 Exercise 9 Question 11 (Page No. 394)
Implement the circuit defined below with NAND SR latch. An asynchronous sequential circuit has two internal states and one output. The excitation and output functions describing the circuit are as follows. $Y _1 = x _1x _2 + x _1y _2’ + x _2’y _1$ $Y _2 = x _2 + x _1y _1’y _2 + x _1’y _1$ $z = x _2 + y _1$

ajaysoni1924 asked in Digital Logic Apr 8, 2019

by ajaysoni1924

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18

Morris Mano Edition 3 Exercise 9 Question 10 (Page No. 394)
Implement the circuit with defined below with NOR SR latch. an asynchronous circuit is described by the following excitation and output functions: $Y = x _1x _2’ + (x _1 + x _2’)y$ $z = y$

ajaysoni1924 asked in Digital Logic Apr 8, 2019

by ajaysoni1924

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19

Morris Mano Edition 3 Exercise 9 Question 9 (Page No. 394)
For the asynchronous sequential circuit shown in the figure: Derive the boolean functions for the outputs of two SR latches $Y _1 and Y _2$. Note that the S input of the second latch is $x _1’y _1’$. Derive the transition table and output map of the circuit.

ajaysoni1924 asked in Digital Logic Apr 7, 2019

by ajaysoni1924

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20

Morris Mano Edition 3 Exercise 9 Question 8 (Page No. 394)
Convert the circuit of the figure to the asynchronous sequential circuit by removing the clock-pulse(CP) and changes the flip-flops to the SR latches. Derive the transition table and output map of the modified circuit.

ajaysoni1924 asked in Digital Logic Apr 7, 2019

by ajaysoni1924

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21

Morris Mano Edition 3 Exercise 9 Question 7 (Page No. 394)
Analyze the T flip-flop shown in the figure. Obtain the transition table and show that the circuit is unstable when both T and CP are equal to 1.

ajaysoni1924 asked in Digital Logic Apr 7, 2019

by ajaysoni1924

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Morris Mano Edition 3 Exercise 9 Question 6 (Page No. 393)
Investigate the transition table of the figure and determine all the race conditions whether they are critical or not critical. Also, determine whether there are any cycles.

ajaysoni1924 asked in Digital Logic Apr 7, 2019

by ajaysoni1924

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23

Morris Mano Edition 3 Exercise 9 Question 5 (Page No. 393)
Convert the flow table of the figure into a transition table by assigning the following binary values to the states: a = 00, b = 11, and c = 10. Assign values to the extra fourth state to avoid critical races. Assign output to the don’t care states to avoid momentary false output. Derive the logic diagram of the circuit.

ajaysoni1924 asked in Digital Logic Apr 7, 2019

by ajaysoni1924

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24

Morris Mano Edition 3 Exercise 9 Question 4 (Page No. 392)
An asynchronous sequential circuit has two internal states and one output. The excitation and output functions describing the circuit are as follows. $Y _1 = x _1x _2 + x _1y _2' + x _2'y _1$ ... Draw the logic diagram of the circuit. Derive the transition table and the output map. Obtain a flow table for the circuit.

ajaysoni1924 asked in Digital Logic Apr 7, 2019

by ajaysoni1924

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25

Morris Mano Edition 3 Exercise 9 Question 3 (Page No. 392)
an asynchronous circuit is described by the following excitation and output functions: $Y = x _1x _2’ + (x _1 + x _2’)y$ $z = y$ Draw the logic diagram of the circuit. Derive the transition table and the output map. obtain a two-state flow table. Describe in the words the behavior of the circuit.

ajaysoni1924 asked in Digital Logic Apr 7, 2019

by ajaysoni1924

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Morris Mano Edition 3 Exercise 9 Question 2 (Page No. 392)
Derive a transition table for the asynchronous sequential circuit given in the figure. Determine the sequence of the internal states $y _1Y _2$ for the following sequence of the input $x _1x _2$: 00,10,11,01,11,10,00.

ajaysoni1924 asked in Digital Logic Apr 7, 2019

by ajaysoni1924

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27

Morris Mano Edition 3 Exercise 9 Question 1 (Page No. 392)
Explain the difference between synchronous and asynchronous sequential circuits. Define fundamental mode operation. Explain the difference between stable and unstable states. what is the difference between an internal state or a total state?

ajaysoni1924 asked in Digital Logic Apr 7, 2019

by ajaysoni1924

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28

Morris Mano Edition 3 Exercise 7 Question 42 (Page No. 306)
It is necessary to formulate the hamming code for four data bits $D _3, D _5, D _6 and D _7$ together with three parity bits $P _1, P _2 and P _3$. evaluate the 7-bit composite code word for the data word 0010. Evaluate ... error detection in the code. Assume that error occurs in the bit $D _5 and P _2$. Show how the error is detected.

ajaysoni1924 asked in Digital Logic Apr 6, 2019

by ajaysoni1924

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29

Morris Mano Edition 3 Exercise 7 Question 41 (Page No. 306)
How many parity check bits must be included with the data word to achieve single-bit error correction and double error correction when data words are as follows: 16 bits 32 bits 48 bits

ajaysoni1924 asked in Digital Logic Apr 6, 2019

by ajaysoni1924

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30

Morris Mano Edition 3 Exercise 7 Question 40 (Page No. 306)
A 12-bit hamming code word 8-bits of data and 4 parity bits are read from the memory. What was the original 8-bit data word that was written into the memory if the 12-bits word read out are as follows: 000011101010 101110000110 101111110100

ajaysoni1924 asked in Digital Logic Apr 6, 2019

by ajaysoni1924

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