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Recent activity by goldenface
9
answers
1
GATE CSE 2019 | Question: 22
Two numbers are chosen independently and uniformly at random from the set $\{1,2,\ldots,13\}.$ The probability (rounded off to $3$ decimal places) that their $4\text{-bit}$ (unsigned) binary representations have the same most significant bit is ___________.
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in
Digital Logic
Feb 9, 2021
19.9k
views
gatecse-2019
numerical-answers
digital-logic
number-representation
probability
1-mark
2
answers
2
GATE IT 2004 | Question: 10
What is the minimum size of ROM required to store the complete truth table of an $8-bit \times 8-bit$ multiplier? $32 K \times 16$ bits $64 K \times 16$ bits $16 K \times 32$ bits $64 K \times 32$ bits
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in
Digital Logic
Feb 9, 2021
6.5k
views
gateit-2004
digital-logic
normal
rom
9
answers
3
GATE CSE 2016 Set 1 | Question: 33
Consider a carry look ahead adder for adding two $n$-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is $\Theta (1)$ $\Theta (\log(n))$ $\Theta (\sqrt{n})$ $\Theta (n)$)
answered
in
Digital Logic
Feb 9, 2021
31.0k
views
gatecse-2016-set1
digital-logic
adder
normal
7
answers
4
GATE CSE 2013 | Question: 37
In an IPv4 datagram, the $M$ bit is $0$, the value of $HLEN$ is $10$, the value of total length is $400$ and the fragment offset value is $300$. The position of the datagram, the sequence numbers of the first and the last bytes of the payload, ... , $2400$ and $2789$ First fragment, $2400$ and $2759$ Last fragment, $2400$ and $2759$ Middle fragment, $300$ and $689$
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in
Computer Networks
Feb 8, 2021
29.6k
views
gatecse-2013
computer-networks
ip-addressing
normal
9
answers
5
GATE CSE 2015 Set 2 | Question: 52
$\text{Host A}$ sends a $\text{UDP}$ datagram containing $8880\text{ bytes}$ of user data to $\text{host B}$ over an $\text{Ethernet LAN}.$ Ethernet frames may carry data up to $1500\text{ bytes (i.e. MTU = 1500 bytes)}.$ Size of $\text{UDP}$ ... be the contents of offset field in the last fragment? $6$ and $925$ $6$ and $7400$ $7$ and $1110$ $7$ and $8880$
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in
Computer Networks
Feb 8, 2021
25.6k
views
gatecse-2015-set2
computer-networks
ip-packet
normal
4
answers
6
NIELIT 2017 OCT Scientific Assistant A (IT) - Section D: 10
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns
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in
Digital Logic
Feb 1, 2021
944
views
nielit2017oct-assistanta-it
digital-logic
sequential-circuit
flip-flop
digital-counter
2
answers
7
GATE CSE 2020 | Question: 38
An organization requires a range of IP address to assign one to each of its $1500$ computers. The organization has approached an Internet Service Provider (ISP) for this task. The ISP uses CIDR and serves the requests from the available IP address space $202.61.0.0/17$. The ... $\text{III}$ only $\text{III}$ and $\text{IV}$ only $\text{I}$ and $\text{IV}$ only
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in
Computer Networks
Feb 1, 2021
24.2k
views
gatecse-2020
computer-networks
subnetting
2-marks
4
answers
8
GATE CSE 2017 Set 2 | Question: 42
The next state table of a $2-$ ... $T_1 = Q_1+Q_0, \quad T_0= \bar{Q_1} \bar{Q_0}$ $T_1 = \bar{Q_1}Q_0, \quad T_0= Q_1 + Q_0$
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in
Digital Logic
Feb 1, 2021
11.1k
views
gatecse-2017-set2
digital-logic
digital-counter
6
answers
9
GATE CSE 2017 Set 1 | Question: GA-9
Arun, Gulab, Neel and Shweta must choose one shirt each from a pile of four shirts coloured red, pink, blue and white respectively. Arun dislikes the colour red and Shweta dislikes the colour white. Gulab and Neel like all the colours. In how many different ways ... the shirts so that no one has a shirt with a colour he or she dislikes? $21$ $18$ $16$ $14$
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in
Quantitative Aptitude
Jan 31, 2021
10.0k
views
gatecse-2017-set1
combinatory
quantitative-aptitude
3
answers
10
GATE CSE 2013 | Question: 49
The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have atmost two source operands and one destination operand. Assume that all variables are dead after this code segment. ... without any spill to memory? Do not apply any optimization other than optimizing register allocation. 3 4 5 6
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in
Compiler Design
Jan 30, 2021
6.8k
views
out-of-syllabus-now
gatecse-2013
normal
compiler-design
target-code-generation
code-optimization
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