in Digital Logic
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1 vote
1 vote

Consider the complemented circuit shown below:

If the initial value of the output Q1 Q0 is 00, then the next three values of Q1 Q0 are:-

  1.   10,01,01,00
  2.   10,01,11,00
  3.   10,01,00,01
  4.   10,01,10,00

Doubt:- I am getting a sequence which is not matching with any of the option

in Digital Logic
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11 Comments

the sequence is: 00->11->01->10->00.......

none are correct.

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Plz, check again  M getting 10,01,11,00 which is B

It is asynchronous ckt so why 00 -> 11 possible
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@Anu sir,

what  seqnc i have given, i think it is correct, are you considering the fact that for T flip working clock pulse is when transition (Q1:0->1) occur
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When Q1 is 1 then only 2nd FF work . like initial condition is 00

Q1= 0 and Q0 =0

so 1st FF Work for every clock

Output for 1st time is Q1= 1(since 1 is input to D FF)  and Q0 =0(since clock input is 0 but it is work on 1)
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@Anu sir, what you are saying, it is for level trigger.....but in qsn it is given edge trigger..

symbol for level trigger clock(-----)// straight line

symbol for edge trigger clock(---->)// straight line with arrow head.
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yes nitish . sorry for that.
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@joshi_nitish

I am also getting same sequence !!

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this is gate question but options are changed.
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I am getting 00->11->01->10->00

WHAT IS THE CORRECT ANSWER
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None of them are correct.
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edited by

$Q_{1Next} = D = Q_{1}';\:\text{for every clock}$

$Q_{0Next}=Q_{0}'\:;$ When $Q_{1}:0\rightarrow 1(\text{Positve edge triggered})$

$Q_{1}$ $Q_{0}$ $Q_{1Next}$ $Q_{0Next}$
0 0 1 1
0 1 1 0
1 0 0 0
1 1 0 1

 

State diagram:

 

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1 Answer

1 vote
1 vote

I am getting 00-->10-->01-->11-->01 again.

 please correct me.

 

 

1 comment

@lokeshsharma123456

Your answer is correct :)
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