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Recent questions tagged pipelining

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151

Speedup in coa
In a processor each instruction execution completes in 4 clock cycle with 2.5 gigahertz. The same processor is transformed into a pipelined processor with five stages operated with 2.0 gigahertz what is the speedup achieved.

Nandkishor3939 asked in CO and Architecture Jan 19, 2019

by Nandkishor3939

774 views

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1 answer

152

ME TEST SERIES QUESTION ON PIPELINE

Shankar Kakde asked in CO and Architecture Jan 16, 2019

by Shankar Kakde

437 views

1 vote

1 answer

153

MadeEasyTest
6 stage pipeline without any branch prediction pipeline cycle time is 4ns used to execute program segment with 20 instruction (i-1 to i-20) i5 is unconditional TOC instruction which transfer the control to i-18.Pipeline target address is available in 4th stage then Program execution time is …..

Abhisek Tiwari 4 asked in CO and Architecture Jan 16, 2019

by Abhisek Tiwari 4

282 views

1 vote

1 answer

154

Applied Course | Mock GATE | Test 1 | Question: 61
Consider a pipelined processor, which has $5$ stages Fetch, Decode, Execute, memory and Write back with latencies $300 \: ms$, $400 \: ms$, $350 \: ms$, $550 \: ms$ and $100 \: ms$ respectively. What is the latency of an instruction? (Assume ... $1700 \: ms$ $1720 \: ms$ $2750 \: ms$ $2850 \: ms$

Applied Course asked in CO and Architecture Jan 16, 2019

by Applied Course

501 views

1 vote

1 answer

155

PIPELINING
Consider the following sequence of instructions executed on the five-stage pipelined processor: LW $1, 30($6) ADD $2, $4, $2 ADD $1, $3, $5 SW $2, 20($4) ADD $1, $1, $4 Assuming there is no forwarding, calculate the number of clock cycles needed to execute above program ?

Himanshu Kashyap asked in CO and Architecture Jan 16, 2019

by Himanshu Kashyap

769 views

2 votes

1 answer

156

MadeEasy Test Series 2019: CO & Architecture - Pipelining
5 stage pipeline → 3,6,5,8,4 latencies(in ns).What is average CPI of non pipelined CPU when speed up achieved by to pipeline is 4 ? (ans = 1.23)

Satbir asked in CO and Architecture Jan 16, 2019

by Satbir

879 views

0 votes

2 answers

157

made easy
A hypothetical 5 stage pipeline processor is designed in which branch is predicted at 3rd stage and each stage takes 1 cycle to compute its tasks. If f is the probability of an instruction being branch instruction then the value of f such that speedup is atleast 3 is____

Harshit Bajpai asked in CO and Architecture Jan 14, 2019

by Harshit Bajpai

1.1k views

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0 answers

158

Test series
#Pipelining Please clear my doubt. In a 5 stage pipelining (IF, ID, EX, MA, WB) there are 5 instruction given. Instruction 1 : R2 ← R0 + R1; Instruction 2 : R1 ← R2 - R1; Instruction 3 : R0 ← R2 - R0; Instruction 4 : R2 ← ... My understanding is whenever dependency is there b/w instruction, ID phase of Next instruction will occur after EX phase of previous Instruction. It is correct ?

aditya dhanraj asked in CO and Architecture Jan 13, 2019

by aditya dhanraj

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159

madeeasy
Consider a 5 stage pipeline with IF , ID, EX, WB and MA having latencies (in ms) 3,8,5,6,4. What is average CPI of non pipeline CPU when speed up achieved by to pipeline is 4? I think answer is wrong For non pipe line total time = Total number of ... * time for each cycle calculation For pipeline version total time = Total number of instruction * max(3,8,5,6,4) So No role of CPI

mehul vaidya asked in CO and Architecture Jan 12, 2019

by mehul vaidya

318 views

0 votes

0 answers

160

ME TEST SERIES DOUBT
A CPU Manufacturer company has two designs p1 and p2 for a synchronous pipeline processor. P1 has 5 pipeline stages with execution times of 3 ns, 4 ns, 3 ns, 2 ns, 4 ns while the design P2 has 6pipeline stage with 3 ns each (execution time). The time that can be saved by P2 over P1 for executing 1000 Instructions is _____________ ns. iam getting answer 997 but they give 1001

Deepanshu asked in CO and Architecture Jan 11, 2019

366 views

1 vote

4 answers

161

Madeeasy- Types of Dependencies
Please clarify along with the names.

Markzuck asked in CO and Architecture Jan 9, 2019

1.3k views

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0 answers

162

Madeeasy COA Ques
Please explain.

Shubham Kumar Gupta asked in CO and Architecture Jan 9, 2019

by Shubham Kumar Gupta

378 views

1 vote

3 answers

163

ME TEST SERIES
A hypothetical 5 stage pipeline processor is designed in which branch is predicted at 3rd stage and each stage takes 1 cycle to compute its task. If p is a the probability of an instruction being a branch instruction then the value of p such that speed up is atleast 3 is ________. (Upto 2 decimal places)

himgta asked in CO and Architecture Jan 9, 2019

by himgta

1.7k views

0 votes

1 answer

164

How many stall cycles are caused due to each incorrect branch prediction?
The title says it all: How many stall cycles are caused due to each incorrect branch prediction? Additional details you might need: Branch is executed in execution stage of pipeline (but will love to know what happens when branch is executed in decode stage too)

Raj Singh 1 asked in CO and Architecture Jan 9, 2019

755 views

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0 answers

165

garimanand asked in CO and Architecture Jan 6, 2019

167 views

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0 answers

166

ME OTS : Pipelining
Consider the following statements (I) Execution time for single instruction on six stage pipelined CPU is less than or equal to identical non- pipelined CPU. (ii) In a uniform delay pipeline execution time for a single instruction is equal to the ... if stage delay exist then for single execution, pipeline time will not be equal. Hence 2nd statement wont be true always.

HeadShot asked in CO and Architecture Jan 5, 2019

1.2k views

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0 answers

167

UPPCL AE 2018:50
Assume that we test the performance of two processors, $\text{P}_{1}$ and $\text{P}_{2},$ on a program. We find the following about each: Processor $\text{P}_{1}$ has a $\text{CPI}$ of $2$ and executes $2$ billion instructions per ... $\text{B}$ Not enough information to tell Processor $\text{A}$ They have equal performance

admin asked in CO and Architecture Jan 5, 2019

by admin

262 views

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0 answers

168

UPPCL AE 2018:44
In an instruction execution pipeline, the earliest that the instruction $\text{TLB}$ and data $\text{TLB}$ can be accessed are Memory stage and memory stage respectively Memory stage and execute stage respectively Fetch stage and fetch stage respectively Fetch stage and memory stage respectively

admin asked in CO and Architecture Jan 5, 2019

by admin

216 views

0 votes

1 answer

169

Computer Org and A1
Total: n instruction Total conditional statement probability :p and True condition probability:q i)Branch is known at end of t satge Effective CPI = [npq*(t+1) + (n-npq)*1)]/n OR ii) Penality is t stall cycle same i.e Effective CPI = [npq*(t+1) + (n-npq)*1)]/n OR iii) Effective CPI= 1+ stall freq*stall penality =1+pq*t am i correct???

Abhisek Tiwari 4 asked in CO and Architecture Jan 5, 2019

by Abhisek Tiwari 4

290 views

0 votes

2 answers

170

Data forwarding in pipelining
Data forwarding is used to avoid which type of conflict?? (1) RAW (2) WAR (3) WAW (4) RAR

Abhilash Mishra asked in CO and Architecture Jan 2, 2019

by Abhilash Mishra

1.3k views

1 vote

2 answers

171

Speed up factor
Pipeline system has 4 stages and each stage takes 10ns. 30% instructions are branch instructions .each branch instruction introduces delay of 3 cycle. What is speed up factor compare to same non pipelines, If there are 1000 instructions.

Alina asked in CO and Architecture Jan 1, 2019

by Alina

2.9k views

0 votes

1 answer

172

Pipelining
Why pipelining cannot operate at its maximum theoretical speed? Maximum theoretical is when we say that it takes same time to process an instruction in pipeline and non pipeline circuit. So why pipelining cannot operate at its maximum theoretical speed?

Alina asked in CO and Architecture Dec 31, 2018

by Alina

491 views

0 votes

1 answer

173

Avoiding pipeline Hazards
Please Confirm.

smsubham asked in CO and Architecture Dec 27, 2018

456 views

1 vote

1 answer

174

GATE Overflow | Mock GATE | Test 1 | Question: 61
A $5$ stage pipeliine is used to overlap all the instructions except the branch instructions. The target of the branch can't be fetched till the current instruction is completed. What is the Throughput (in MIPS) of the system if $20\%$ of the ... The pipeline clock rate is $0.1 \: GHz$. Branch penalty is $4$ cycles. (Upto $2$ decimal place).

Ruturaj Mohanty asked in CO and Architecture Dec 27, 2018

by Ruturaj Mohanty

1.1k views

0 votes

1 answer

175

Self doubt
If the time taken by a task to get completed is same in the pipeline and non pipeline circuits, then how the time taken to complete the task in non pipeline = k* time taken to complete the task in pipeline where k is no. of segments in the pipeline?

Nivedita Singh asked in CO and Architecture Dec 27, 2018

by Nivedita Singh

361 views

0 votes

1 answer

176

Prateek Raghuvanshi asked in CO and Architecture Dec 25, 2018

by Prateek Raghuvanshi

421 views

1 vote

1 answer

177

ME test series
Consider a pipeline 'x', consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 6 ns, 5 ns, 8 ns and 1 ns. The alternative pipeline 'y' contain the same number of stages but EX stage is divided ... the instructions which are memory based instructions, what is the ratio of speedup of x to speedup of y? 0.727 0.902 0.665 0.825

newdreamz a1-z0 asked in CO and Architecture Dec 25, 2018

by newdreamz a1-z0

740 views

0 votes

2 answers

178

MadeEasy Test Series: CO & Architecture - Pipelining
here why to take stall at the highlighted cell as its OPERAND FORWARDING and unless mentioned its EX-EX and its being followed without stall also, please clarify how to understand where Operand Forwarding is to be applied in such generalized cases., Thanks in advance :)

Markzuck asked in CO and Architecture Dec 25, 2018

966 views

0 votes

0 answers

179

CO pipelining
consider a 4-stage pipeline (IF, ID, EX, WB) used to execute the following code. All the instructions are spending 1 cycle in all the stags but MUL takes 4 cycles. Div takes 3 cycles in EX stages. The pipeline uses operand forwarding as an optimization a- how many cycles are required to complete ... ? I1 : MUL r0 , r1 , r2 I2 : DIV r3 , r1 , r2 I3: SUB r4, r3, r2 I4: ADD r5, r4, r1

hitendra singh asked in CO and Architecture Dec 24, 2018

by hitendra singh

988 views

1 vote

1 answer

180

abhishekmehta4u asked in CO and Architecture Dec 22, 2018

by abhishekmehta4u

774 views

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Recent questions tagged pipelining