Login
Register
@
Dark Mode
Profile
Edit my Profile
Messages
My favorites
Register
Activity
Q&A
Questions
Unanswered
Tags
Subjects
Users
Ask
Previous Years
Blogs
New Blog
Exams
Dark Mode
Recent questions tagged synchronous-asynchronous-circuits
0
votes
0
answers
31
Morris Mano Edition 3 Exercise 7 Question 34 (Page No. 305)
Word number 535 in the memory shown in the figure contains the binary equivalent of 2209. List the 10 bit address and 16-bit memory content of the word.
ajaysoni1924
asked
in
Digital Logic
Apr 6, 2019
by
ajaysoni1924
386
views
digital-logic
morris-mano
sequential-circuit
synchronous-asynchronous-circuits
0
votes
0
answers
32
Morris Mano Edition 3 Exercise 7 Question 33 (Page No. 305)
The following memory units are specified by the number of words times the number of bits per word. How many address lines and Input output data lines are needed in each case given below? $2K \times 16$; $64K \times 8$; $16M \times 32$; $96K \times 12$;
ajaysoni1924
asked
in
Digital Logic
Apr 6, 2019
by
ajaysoni1924
257
views
digital-logic
morris-mano
sequential-circuit
synchronous-asynchronous-circuits
0
votes
0
answers
33
Morris Mano Edition 3 Exercise 7 Question 30 (Page No. 305)
Show the circuit and the timing diagram for generating six repeated timing signals, $T _0$ through $T _5$.
ajaysoni1924
asked
in
Digital Logic
Apr 6, 2019
by
ajaysoni1924
187
views
digital-logic
morris-mano
sequential-circuit
synchronous-asynchronous-circuits
digital-circuits
0
votes
0
answers
34
Morris Mano Edition 3 Exercise 7 Question 29 (Page No. 305)
Add four 2-input AND gates to the circuit of the figure. One input in each gate is connected to one output of the decoder. The other input in each gate is connected to the clock. Label the outputs of the AND gate as $P _0,P _1,P _2, and P _3$. Show the timing diagram of the for P outputs.
ajaysoni1924
asked
in
Digital Logic
Apr 6, 2019
by
ajaysoni1924
191
views
digital-logic
morris-mano
sequential-circuit
synchronous-asynchronous-circuits
0
votes
0
answers
35
Morris Mano Edition 3 Exercise 7 Question 28 (Page No. 305)
Using a start signal as in the figure , construct a word time control that stays on for a period of 16 clock pulses.
ajaysoni1924
asked
in
Digital Logic
Apr 6, 2019
by
ajaysoni1924
298
views
digital-logic
morris-mano
sequential-circuit
synchronous-asynchronous-circuits
0
votes
0
answers
36
Morris Mano Edition 3 Exercise 7 Question 23 (Page No. 304)
Design a synchronous BCD counter with JK flip-flops
ajaysoni1924
asked
in
Digital Logic
Apr 6, 2019
by
ajaysoni1924
418
views
digital-logic
morris-mano
sequential-circuit
digital-counter
synchronous-asynchronous-circuits
0
votes
0
answers
37
Morris Mano Edition 3 Exercise 7 Question 2,3 (Page No. 303)
Change the asynchronous-clear-circuit of the figure to the synchronous-clear-circuit, The modified register will have parallel load capability and asynchronous clear capability, but no asynchronous clear circuit. The register is cleared ... input CP goes through a negative transition while the D input of all the flip-flops are 0.
ajaysoni1924
asked
in
Digital Logic
Apr 6, 2019
by
ajaysoni1924
935
views
digital-logic
morris-mano
sequential-circuit
synchronous-asynchronous-circuits
registers
0
votes
0
answers
38
Morris Mano Edition 3 Exercise 7 Question 1 (Page No. 303)
Include a 2-input NAND gate with the register of the figure and connect the gate output to CP inputs of all the flip-flops. One input of the NAND gate receives input from the clock-pulse-generator. Another input of NAND gate provides parallel load control. Explain the operation of the modified register.
ajaysoni1924
asked
in
Digital Logic
Apr 6, 2019
by
ajaysoni1924
522
views
digital-logic
morris-mano
sequential-circuit
synchronous-asynchronous-circuits
registers
0
votes
0
answers
39
Morris Mano Edition 3 Exercise 6 Question 25 (Page No. 255)
Design the following non-binary sequence counter as specified in each case. Treat the unused states as don't cares conditions. Analyze the final circuit to ensure that it is self-correcting. If your design produces a non-self-correcting ... . Design a counter with the following repeated binary sequence 0,1,3, 7,6,4. Use T flip-flops.
ajaysoni1924
asked
in
Digital Logic
Apr 6, 2019
by
ajaysoni1924
1.7k
views
digital-logic
morris-mano
sequential-circuit
synchronous-asynchronous-circuits
digital-counter
1
vote
1
answer
40
Morris Mano Edition 3 Exercise 6 Question 24 (Page No. 255)
Design the sequential circuit specified by the following state diagram using T flip-flop.
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
7.7k
views
digital-logic
morris-mano
sequential-circuit
synchronous-asynchronous-circuits
0
votes
0
answers
41
Morris Mano Edition 3 Exercise 6 Question 23 (Page No. 255)
Design a sequential circuit specified by the following state transition diagram. using RS flip-flop.
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
751
views
digital-logic
morris-mano
sequential-circuit
synchronous-asynchronous-circuits
2
votes
0
answers
42
Morris Mano Edition 3 Exercise 6 Question 22 (Page No. 255)
A sequential circuit has three flip-flops, A, B, C; one input, x; one output, y; The state diagram is shown in the figure. The circuit is to be designed by treating the unused state as don't care conditions. The final circuit ... analyzed to ensure that it is self-correcting. Use D flip-flop in the design. USe JK flip-flops in the design .
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
1.9k
views
digital-logic
morris-mano
sequential-circuit
flip-flop
synchronous-asynchronous-circuits
0
votes
0
answers
43
Morris Mano Edition 3 Exercise 6 Question 21 (Page No. 255)
Design a sequential circuit with two JK flip-flops, A and B and two inputs, E and x. If E = 0 the circuit remains in the same state regardless of the value of x. When E = 1and x = 1, the circuit goes through the transactions from ... = 1 and x = 0 the circuit goes through the transactions from 00 to 11 to 10 to 01 back to 00, and repeats.
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
352
views
digital-logic
morris-mano
sequential-circuit
flip-flop
synchronous-asynchronous-circuits
0
votes
0
answers
44
Morris Mano Edition 3 Exercise 6 Question 20 (Page No. 255)
Design a sequential circuit with two D flip-flops A and B and one input, x. When x = 0 the state of the circuit remains the same. When x =1 circuit goes through the state transition from 00 to 01 to 1 to 10 back to 00 and, repeats.
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
303
views
digital-logic
morris-mano
sequential-circuit
flip-flop
synchronous-asynchronous-circuits
0
votes
0
answers
45
Morris Mano Edition 3 Exercise 6 Question 19 (Page No. 254)
Convert a D flip-flop to JK flip-flop by including input gates to the D flip-flop. The gates need for the input of the D flip-flop can be determined by means of the sequential circuit design procedure. The sequential circuit to be considered will have one D flip-flop and two inputs, J and K.
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
826
views
digital-logic
morris-mano
sequential-circuit
synchronous-asynchronous-circuits
flip-flop
0
votes
0
answers
46
Morris Mano Edition 3 Exercise 6 Question 18 (Page No. 254)
Analyze the circuit in the following figure and show that it is equivalent to T flip-flop.
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
957
views
digital-logic
morris-mano
sequential-circuit
flip-flop
synchronous-asynchronous-circuits
0
votes
1
answer
47
Morris Mano Edition 3 Exercise 6 Question 15,16 (Page No. 254)
Starting from a state of the state table given below find out the output sequence generated with an input sequence 01110010011. reduce the same table and repeat the same sequence with the given input sequence. Show that same output is obtained.
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
2.0k
views
digital-logic
sequential-circuit
synchronous-asynchronous-circuits
circuit-output
2
votes
1
answer
48
Morris Mano Edition 3 Exercise 6 Question 14 (Page No. 254)
Reduce the number of states in the following state table and tabulate the reduced state table.
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
5.3k
views
digital-logic
sequential-circuit
synchronous-asynchronous-circuits
circuit-output
1
vote
0
answers
49
Morris Mano Edition 3 Exercise 6 Question 13 (Page No. 254)
Starting from state 00 in the state transition diagram of the figure. Determine the state transitions and output sequence that will be generated when the input sequence of 010110111011110 is applied.
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
2.1k
views
digital-logic
sequential-circuit
circuit-output
synchronous-asynchronous-circuits
0
votes
2
answers
50
Synchronous Counter Circuit
In the given synchronous Counter circuit, initially all Outputs are Reset. It is required to replace FF2 with AB Flip Flop. The FF2 inputs would be:- A. A = Q1 and B = Q1' B. A = Q1' and B = Q1' C. A = Q1.Q0 and B = Q1.Q0 D. A = Qo' and B = Qo'
Na462
asked
in
Digital Logic
Oct 10, 2018
by
Na462
465
views
digital-logic
synchronous-asynchronous-circuits
digital-counter
1
vote
1
answer
51
Synchronous Counter
Na462
asked
in
Digital Logic
Oct 1, 2018
by
Na462
1.1k
views
digital-logic
synchronous-asynchronous-circuits
digital-counter
0
votes
1
answer
52
MadeEasy Test Series: Digital Logic - Synchronous Counter
Consider the following synchronous counter made up of JK,D,T flip flops as in the image! now here why J is taken as Q0' (complement) instead of Q0'' (double complement) you can clearly see a bubble and a q0' ... as it should be so q0'' right? please clarify!
vishnu priyan
asked
in
Digital Logic
Dec 14, 2017
by
vishnu priyan
1.0k
views
digital-logic
made-easy-test-series
digital-counter
synchronous-asynchronous-circuits
1
vote
1
answer
53
Virtual Gate Test Series: Digital Logic - Counter
Manoja Rajalakshmi A
asked
in
Digital Logic
Nov 12, 2017
by
Manoja Rajalakshmi A
355
views
digital-logic
sequential-circuit
synchronous-asynchronous-circuits
ripple-counter
virtual-gate-test-series
2
votes
1
answer
54
MadeEasy Subject Test: Digital Logic - Flip Flop
For synchronous series counter of modulus 256, the propagation delay for each flip flop is 25 nsec and propagation delay of each two input AND gate is 5 nsec. What is the maximum frequency of MOD 256 counter ?(in MHz) a)18.18 b)19.18 c)20. ... makes Frequency = 1/(30 nsec) = 33.33 Mhz? please correct me where I am going wrong. Thanks for your help :)
Kamal Pratap
asked
in
Digital Logic
Oct 10, 2017
by
Kamal Pratap
494
views
made-easy-test-series
digital-logic
synchronous-asynchronous-circuits
clock-frequency-flop
flip-flop
0
votes
0
answers
55
doubt -synchronous counter
what is the correct way to design synchronous counter ?for any arbitrary sequence like 7,3,1,2,5,4,6,7,3,1,2,4,5,6 I simply using state table diagram and by minimization it is easy to design circuit.Also to identify minimum number ... flop in synchronous counter I just calculating number of bits used in counter . pls tell correct approach to solve these type of problems
set2018
asked
in
Digital Logic
Oct 2, 2017
by
set2018
304
views
digital-logic
synchronous-asynchronous-circuits
self-doubt
1
vote
2
answers
56
gate 2014
which is faster, synchronous circuits or asynchronous circuits and why?
Sunil8860
asked
in
Digital Logic
Aug 29, 2017
by
Sunil8860
1.3k
views
digital-logic
synchronous-asynchronous-circuits
asynchronous-circuit
3
votes
1
answer
57
Test by Bikram | Mock GATE | Test 4 | Question: 51
In a synchronous series counter of Modulus $256$, the propagation delay for each $2$ input AND gate is $5$ ns and for each flip-flop is $25$ ns. The maximum frequency of the Mod-256 counter is _____MHz.
Bikram
asked
in
Digital Logic
May 14, 2017
by
Bikram
905
views
tbb-mockgate-4
numerical-answers
digital-logic
clock-frequency
digital-counter
synchronous-asynchronous-circuits
1
vote
3
answers
58
Virtual Gate Test Series: Digital Logic - Asynchronous Counter
Hradesh patel
asked
in
Digital Logic
Oct 8, 2016
by
Hradesh patel
942
views
digital-logic
synchronous-asynchronous-circuits
digital-counter
virtual-gate-test-series
0
votes
2
answers
59
MadeEasy Workbook: Digital Logic - Synchronous Asynchronous Circuits
Payal Rastogi
asked
in
Digital Logic
Dec 25, 2015
by
Payal Rastogi
861
views
digital-logic
synchronous-asynchronous-circuits
made-easy-booklet
23
votes
3
answers
60
GATE CSE 1998 | Question: 16
Design a synchronous counter to go through the following states:$1, 4, 2, 3, 1, 4, 2, 3, 1, 4 \dots $
Kathleen
asked
in
Digital Logic
Sep 26, 2014
by
Kathleen
5.0k
views
gate1998
digital-logic
normal
descriptive
synchronous-asynchronous-circuits
Page:
« prev
1
2
3
next »
Subscribe to GATE CSE 2024 Test Series
Subscribe to GO Classes for GATE CSE 2024
Quick search syntax
tags
tag:apple
author
user:martin
title
title:apple
content
content:apple
exclude
-tag:apple
force match
+apple
views
views:100
score
score:10
answers
answers:2
is accepted
isaccepted:true
is closed
isclosed:true
Recent Posts
Post GATE 2024 Guidance [Counseling tips and resources]
GATE CSE 2024 Result Responses
[Project Contest] Pytorch backend support for MLCommons Cpp Inference implementation
Participating in MLCommons Inference v4.0 submission (deadline is February 23 12pm IST)
IIITH PGEE 2024 Test Series by GO Classes
Subjects
All categories
General Aptitude
(3.5k)
Engineering Mathematics
(10.4k)
Digital Logic
(3.6k)
Programming and DS
(6.2k)
Algorithms
(4.8k)
Theory of Computation
(6.9k)
Compiler Design
(2.5k)
Operating System
(5.2k)
Databases
(4.8k)
CO and Architecture
(4.0k)
Computer Networks
(4.9k)
Artificial Intelligence
(79)
Machine Learning
(48)
Data Mining and Warehousing
(25)
Non GATE
(1.4k)
Others
(2.7k)
Admissions
(684)
Exam Queries
(1.6k)
Tier 1 Placement Questions
(17)
Job Queries
(80)
Projects
(11)
Unknown Category
(870)
64.3k
questions
77.9k
answers
244k
comments
80.0k
users
Recent questions tagged synchronous-asynchronous-circuits
Recent Blog Comments
category ?
Hi @Arjun sir, I have obtained a score of 591 in ...
download here
Can you please tell about IIT-H mtech CSE self...
Please add your admission queries here:...