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User topper98
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Answers by topper98
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votes
31
GATE IT 2004 | Question: 62
A disk has $200$ tracks (numbered $0$ through $199$). At a given time, it was servicing the request of reading data from track $120$, and at the previous request, service was for track $90$ ... Time First) and FCFS (First Come First Serve)? $2$ and $3$ $3$ and $3$ $3$ and $4$ $4$ and $4$
answered
in
Operating System
Mar 23, 2020
10.3k
views
gateit-2004
operating-system
disk-scheduling
normal
5
votes
32
GATE CSE 2013 | Question: 53
A computer uses $46\text{-bit}$ virtual address, $32\text{-bit}$ physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table $\text{(T1)},$ which occupies exactly one ... to guarantee that no two synonyms map to different sets in the processor cache of this computer? $2$ $4$ $8$ $16$
answered
in
Operating System
Mar 23, 2020
30.2k
views
gatecse-2013
normal
operating-system
virtual-memory
0
votes
33
ISRO2014-17
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a $4 \times 6$ array, where each chip is $8\;\text{K} \times 4$ bits? $13$ $15$ $16$ $17$
answered
in
CO and Architecture
Mar 23, 2020
10.4k
views
co-and-architecture
memory-interfacing
isro2014
0
votes
34
NIELIT 2017 July Scientist B (CS) - Section B: 27
Which memory is difficult to interface with processor? Static memory Dynamic memory ROM None of the option
answered
in
CO and Architecture
Mar 23, 2020
1.4k
views
nielit2017july-scientistb-cs
co-and-architecture
memory-interfacing
0
votes
35
UGC NET CSE | December 2018 | Part 2 | Question: 15
Consider the following $\textsf{x}86$ - assembly language instructions: MOV AL, 153 NEG AL The contents of the destination register $AL$ (in $8$-bit binary notation), th status of Carry Flag $(CF)$ and Sign Flag $(SF)$ ... $AL=0110 \: 0110; \: CF=1; \: SF=1$ $AL=0110 \: 0111; \: CF=1; \: SF=0$
answered
in
CO and Architecture
Mar 23, 2020
3.8k
views
ugcnetcse-dec2018-paper2
co-and-architecture
assembly
non-gate
0
votes
36
UGC NET CSE | December 2018 | Part 2 | Question: 19
Consider a system with $2$ level cache. Access times of Level $1$ cache, Level $2$ cache and main memory are $0.5$ ns, $5$ ns and $100$ ns respectively. The hit rates of Level $1$ and Level $2$ caches are $0.7$ and $0.8$ ... access time of the system ignoring the search time within the cache? $35.20$ ns $7.55$ ns $20.75$ ns $24.35$ ns
answered
in
Unknown Category
Mar 23, 2020
3.7k
views
ugcnetcse-dec2018-paper2
0
votes
37
Number of bits - Instruction format
A computer uses a memory unit with 256K words of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part to specify one of 64 ... and an address part. How many bits are there in the operation code, the register code part, and the address part respectively?
answered
in
CO and Architecture
Mar 23, 2020
7.4k
views
co-and-architecture
instruction-format
numerical-answers
0
votes
38
GATE CSE 2001 | Question: 1.10, UGCNET-Dec2012-III: 36
Suppose a processor does not have any stack pointer registers, which of the following statements is true? It cannot have subroutine call instruction It cannot have nested subroutines call Interrupts are not possible All subroutine calls and interrupts are possible
answered
in
CO and Architecture
Mar 23, 2020
18.0k
views
gatecse-2001
co-and-architecture
normal
ugcnetcse-dec2012-paper3
runtime-environment
0
votes
39
UGC NET CSE | December 2013 | Part 3 | Question: 47
The start and stop bits are used in serial communication for error detection error correction synchronization slowing down the communication
answered
in
Computer Networks
Mar 23, 2020
3.8k
views
ugcnetcse-dec2013-paper3
computer-networks
serial-communication
0
votes
40
NEILIT_2016_36
When a subroutine is called, then address of the instruction following the CAL instruction is stored in /on the 1. Stack pointer 2. Program counter 3. Stack 4. Accumulator
answered
in
Unknown Category
Mar 23, 2020
826
views
co-and-architecture
0
votes
41
How many address lines are needed to address each memory locations in a 2048 x 4 memory chip
How many address lines are needed to address each memory locations in a 2048 x 4 memory chip
answered
in
CO and Architecture
Mar 23, 2020
4.9k
views
co-and-architecture
1
vote
42
UGC NET CSE | July 2018 | Part 2 | Question: 100
In 8085 microprocessor, what is the output of following program? LDA 8000H MVI B, 30H ADD B STA 8001 H Read a number from input port and store it in memory Read a number from input device with address 8000H and store it ... location 8001H Load A with data from input device with address 8000H and display it on the output device with address 8001H
answered
in
CO and Architecture
Mar 23, 2020
1.6k
views
ugcnetcse-july2018-paper2
co-and-architecture
8085-microprocessor
microprocessors
0
votes
43
UGC NET CSE | July 2018 | Part 2 | Question: 98
Which of the following mapping is not used for mapping process in cache memory Associative mapping Direct mapping Set-Associative mapping Segmented - page mapping
answered
in
CO and Architecture
Mar 23, 2020
12.0k
views
ugcnetcse-july2018-paper2
co-and-architecture
cache-memory
0
votes
44
UGC NET CSE | July 2018 | Part 2 | Question: 97
Match the items in $\textbf{List-I}$ and $\textbf{List-II}$ ... $\text{(a)-(iii), (b)-(i), (c)-(ii)}$ $\text{(a)-(iii), (b)-(iv), (c)-(ii)}$
answered
in
CO and Architecture
Mar 23, 2020
2.6k
views
ugcnetcse-july2018-paper2
co-and-architecture
assembly
interrupts
0
votes
45
UGC NET CSE | July 2018 | Part 2 | Question: 91
CMOS is a computer chip on the motherboard, which is RAM ROM EPROM Auxillary storage
answered
in
CO and Architecture
Mar 23, 2020
1.1k
views
ugcnetcse-july2018-paper2
co-and-architecture
cmos
0
votes
46
ISRO2014-14
There are 200 tracks on a disc platter and the pending requests have come in the order - 36, 69, 167, 76, 42, 51, 126, 12 and 199. Assume the arm is located at the 100th track and moving towards track 200. If sequence of disc access is 126, 167, ... , 36, 42, 51, 69 and 76 then which disc access scheduling policy is used? Elevator Shortest seek-time first C-SCAN First Come First Served
answered
in
Operating System
Mar 23, 2020
4.9k
views
disk-scheduling
isro2014
operating-system
0
votes
47
ISRO2014-1
Consider a $33$ MHz cpu based system. What is the number of wait states required if it is interfaced with a $60$ ns memory? Assume a maximum of $10$ ns delay for additional circuitry like buffering and decoding. $0$ $1$ $2$ $3$
answered
in
CO and Architecture
Mar 23, 2020
8.6k
views
co-and-architecture
isro2014
memory-interfacing
0
votes
48
ISRO-2013-14
A processor is fetching instructions at the rate of $1$ MIPS. A DMA module is used to transfer characters to RAM from a device transmitting at $9600$ bps. How much time will the processor be slowed down due to DMA activity? $9.6$ms $4.8$ms $2.4$ms $1.2$ms
answered
in
CO and Architecture
Mar 23, 2020
7.2k
views
isro2013
dma
0
votes
49
ISRO-2013-15
A pipeline $P$ operating at $400$ MHz has a speedup factor of $6$ and operating at $70$% efficiency. How many stages are there in the pipeline? $5$ $6$ $8$ $9$
answered
in
CO and Architecture
Mar 23, 2020
8.6k
views
isro2013
co-and-architecture
pipelining
0
votes
50
ISRO-2013-16
How much speed do we gain by using the cache, when cache is used $80$% of the time? Assume cache is faster than main memory. $5.27$ $2.00$ $4.16$ $6.09$
answered
in
CO and Architecture
Mar 23, 2020
10.2k
views
isro2013
co-and-architecture
cache-memory
0
votes
51
ISRO-2013-35
How many number of times the instruction sequence below will loop before coming out of the loop? MOV AL, 00H A1: INC AL JNZ A1 1 255 256 Will not come out of the loop.
answered
in
CO and Architecture
Mar 23, 2020
3.9k
views
isro2013
8085-microprocessor
non-gate
0
votes
52
GATE IT 2007 | Question: 6, ISRO2011-25
A processor takes $12$ cycles to complete an instruction I. The corresponding pipelined processor uses $6$ stages with the execution times of $3, 2, 5, 4, 6$ and $2$ cycles respectively. What is the asymptotic speedup assuming that a very large number of instructions are to be executed? $1.83$ $2$ $3$ $6$
answered
in
CO and Architecture
Mar 23, 2020
13.3k
views
gateit-2007
co-and-architecture
pipelining
normal
isro2011
0
votes
53
ISRO2011-16
Consider a direct mapped cache with $64$ blocks and a block size of $16$ bytes. To what block number does the byte address $1206$ map to does not map $6$ $11$ $54$
answered
in
CO and Architecture
Mar 23, 2020
8.9k
views
isro2011
co-and-architecture
cache-memory
0
votes
54
ISRO2011-58
In DMA transfer scheme, the transfer scheme other than burst mode is cycle technique stealing technique cycle stealing technique cycle bypass technique
answered
in
CO and Architecture
Mar 23, 2020
3.5k
views
isro2011
co-and-architecture
io-handling
dma
0
votes
55
ISRO2011-42
The search concept used in associative memory is Parallel search Sequential search Binary search Selection search
answered
in
CO and Architecture
Mar 23, 2020
4.6k
views
isro2011
co-and-architecture
cache-memory
0
votes
56
ISRO2011-41
If a microcomputer operates at $5$ MHz with an $8$-bit bus and a newer version operates at $20$ MHz with a $32$-bit bus, the maximum speed-up possible approximately will be $2$ $4$ $8$ $16$
answered
in
CO and Architecture
Mar 23, 2020
5.8k
views
isro2011
co-and-architecture
cpu
1
vote
57
ISRO2011-39
Two control signals in microprocessor which are related to Direct Memory Access (DMA) are $\textsf{INTR & INTA}$ $\textsf{RD & WR}$ $\textsf{S0 & S1}$ $\textsf{HOLD & HLDA}$
answered
in
CO and Architecture
Mar 23, 2020
6.5k
views
isro2011
co-and-architecture
io-handling
dma
0
votes
58
ISRO2011-5
$\textsf{MOV [BX], AL}$ type of data addressing is called? register immediate register indirect register relative
answered
in
CO and Architecture
Mar 23, 2020
5.6k
views
isro2011
co-and-architecture
addressing-modes
1
vote
59
GATE IT 2004 | Question: 12, ISRO2016-77
Consider a system with $2$ level cache. Access times of Level $1$ cache, Level $2$ cache and main memory are $1$ $ns$, $10$ $ns$, and $500$ $ns$ respectively. The hit rates of Level $1$ and Level $2$ caches are $0.8$ and $0.9$, respectively. What is the average access time of the system ignoring the search time within the cache? $13.0$ $12.8$ $12.6$ $12.4$
answered
in
CO and Architecture
Mar 23, 2020
29.5k
views
gateit-2004
co-and-architecture
cache-memory
normal
isro2016
0
votes
60
ISRO2016-24
In which class of Flynn's taxanomy, Von Neumann architecture belongs to? SISD SIMD MIMD MISD
answered
in
CO and Architecture
Mar 23, 2020
9.7k
views
co-and-architecture
isro2016
instruction-format
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