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User topper98
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Answers by topper98
0
votes
91
ISRO2017-20
Which interrupt in $8085$ Microprocessor is unmaskable? $\textsf{RST 5.5}$ $\textsf{RST 7.5}$ $\textsf{TRAP}$ Both (a) and (b)
answered
in
CO and Architecture
Mar 23, 2020
4.3k
views
isro2017
8085-microprocessor
non-gate
0
votes
92
ISRO2017-19
The most appropriate matching for the following pairs : ... $\text{X-ii, Y-iii, Z-i}$ $\text{X-iii, Y-i, Z-ii}$ $\text{X-ii, Y-i, Z-iii}$
answered
in
CO and Architecture
Mar 23, 2020
3.0k
views
isro2017
co-and-architecture
addressing-modes
match-the-following
easy
1
vote
93
GATE CSE 2000 | Question: 1.10
The most appropriate matching for the following pairs$\begin{array}{ll} \text{X: Indirect addressing} & \text{1: Loops } \\ \text{Y: Immediate addressing } & \text{2: Pointers} \\ \text{Z: Auto decrement addressing } & \text{3: Constants } \\ \end{array}$ is $X - 3, Y - 2, Z - 1$ $X - 1, Y - 3, Z - 2$ $X - 2, Y - 3, Z - 1$ $X - 3, Y - 1, Z - 2$
answered
in
CO and Architecture
Mar 23, 2020
8.4k
views
gatecse-2000
co-and-architecture
easy
addressing-modes
match-the-following
0
votes
94
ISRO2007-53
In the Big-Endian system, the computer stores MSB of data in the lowest memory address of data unit LSB of data in the lowest memory address of data unit MSB of data in the highest memory address of data unit LSB of data in the highest memory address of data unit
answered
in
CO and Architecture
Mar 23, 2020
4.8k
views
isro2007
co-and-architecture
floating-point-representation
little-endian-big-endian
0
votes
95
ISRO2007-19
Assume that each character code consists of $8$ bits. The number of characters that can be transmitted per second through a synchronous serial line at $2400$ baud rate, and with two stop bits is $109$ $216$ $218$ $219$
answered
in
Computer Networks
Mar 23, 2020
7.2k
views
isro2007
serial-communication
1
vote
96
ISRO2007-14
The principal of the locality of reference justifies the use of virtual memory interrupts main memory cache memory
answered
in
CO and Architecture
Mar 22, 2020
5.8k
views
isro2007
co-and-architecture
cache-memory
1
vote
97
ISRO2007-08
A read bit can be read and written by CPU and written by peripheral by peripheral and written by CPU by CPU and written by the peripheral
answered
in
CO and Architecture
Mar 22, 2020
4.7k
views
isro2007
co-and-architecture
registers
0
votes
98
ISRO2018-73
For a multi-processor architecture, in which protocol a write transaction is forwarded to only those processors that are known to possess a copy of newly altered cache line? Snoopy bus protocol Cache coherency protocol Directory based protocol None of the above
answered
in
CO and Architecture
Mar 22, 2020
4.1k
views
isro2018
cache-memory
0
votes
99
ISRO2018-31
A byte addressable computer has a memory capacity of $2$^{m}$KB$ ($k$ bytes) and can perform $2$^{n}$ operations. An instruction involving $3$ operands and one operator needs maximum of: $3m$ bits $3m + n$ bits $m + n$ bits none of the above
answered
in
CO and Architecture
Mar 22, 2020
4.1k
views
isro2018
co-and-architecture
instruction-format
2
votes
100
ISRO2018-65
Of the following, which best characterizes computers that use memory-mapped $\text{I/O}?$ The computer provides special instructions for manipulating $\text{I/O}$ ports $\text{I/O}$ ports are placed at addresses on the bus and are accessed just like ... register and call channel to perform the operation $\text{I/O}$ can be performed only when memory management hardware is turned on
answered
in
CO and Architecture
Mar 22, 2020
3.5k
views
isro2018
co-and-architecture
io-handling
0
votes
101
ISRO2018-34
Micro program is: the name of a source program in micro computers set of microinstructions that defines the individual operations in response to a machine-language instruction a primitive form of macros used in assembly language programming a very small segment of machine code
answered
in
CO and Architecture
Mar 22, 2020
2.5k
views
isro2018
co-and-architecture
microprogramming
0
votes
102
Computer Architecture
The multiplicand register & multiplier register of a hardware circuit implementing booth’s algorithm have (11101) & (1100). The result shall be A. (812) B. (-12) C. (12) D. (-812)
answered
in
CO and Architecture
Mar 21, 2020
3.5k
views
1
vote
103
ISRO2020-77
Consider the following circuit The function by the network above is $\overline{AB}E+EF+\overline{CD}F$ $(\overline{E}+AB\overline{F})(C+D+\overline{F})$ $(\overline{AB}+E)(\overline{E}+\overline{F})(C+D+\overline{F})$ $(A+B)\overline{E} +\overline{EF}+CD\overline{F}$
answered
in
Digital Logic
Mar 21, 2020
2.8k
views
isro-2020
digital-logic
combinational-circuit
circuit-output
normal
2
votes
104
ISRO2020-10
Following Multiplexer circuit is equivalent to Sum equation of full adder Carry equation of full adder Borrow equation for full subtractor Difference equation of a full subtractor
answered
in
Digital Logic
Mar 21, 2020
2.7k
views
isro-2020
digital-logic
combinational-circuit
multiplexer
normal
10
votes
105
ISRO2020-9
In a $8$-bit ripple carry adder using identical full adders, each full adder takes $34$ ns for computing sum. If the time taken for $8$-bit addition is $90$ ns, find time taken by each full adder to find carry. $6$ ns $7$ ns $10$ ns $8$ ns
answered
in
Digital Logic
Mar 21, 2020
3.4k
views
isro-2020
digital-logic
combinational-circuit
adder
normal
1
vote
106
ISRO2020-12
If $ABCD$ is a $4$-bit binary number, then what is the code generated by the following circuit? BCD code Gray code $8421$ code Excess-$3$ code
answered
in
Digital Logic
Mar 21, 2020
3.1k
views
isro-2020
digital-logic
combinational-circuit
circuit-output
normal
3
votes
107
ISRO2020-11
Minimum number of NAND gates required to implement the following binary equation $Y = (\overline{A}+\overline{B})(C+D)$ $4$ $5$ $3$ $6$
answered
in
Digital Logic
Mar 21, 2020
5.3k
views
isro-2020
digital-logic
combinational-circuit
circuit-output
normal
2
votes
108
ISRO2020-5
An array of $2$ ...
answered
in
CO and Architecture
Mar 21, 2020
3.7k
views
isro-2020
co-and-architecture
floating-point-representation
normal
little-endian-big-endian
0
votes
109
NIELIT 2017 OCT Scientific Assistant A (CS) - Section B: 22
If the original size of data is $40$ then after adding error detection redundancy bit the size of data length is $26$ $36$ $46$ $56$
answered
in
Computer Networks
Mar 21, 2020
6.8k
views
nielit2017oct-assistanta-cs
computer-networks
error-detection
0
votes
110
NIELIT 2017 DEC Scientist B - Section B: 46
The number of integers between $1$ and $500$(both inclusive) that are divisible by $3$ or $5$ or $7$ is _________. $269$ $270$ $271$ $272$
answered
in
Set Theory & Algebra
Mar 19, 2020
967
views
nielit2017dec-scientistb
discrete-mathematics
set-theory&algebra
inclusion-exclusion
1
vote
111
NIELIT 2017 DEC Scientist B - Section B: 7
Let $G$ be a grammar in CFG and let $W_1,W_2\in L(G)$ such that $\mid W_1\mid=\mid W_2\mid$ then which of the following statements is true? Any derivation of $W_1$ has exactly the same number of steps as any derivation ... $W_1$ may be shorter than the derivation of $W_2$ None of the options
answered
in
Theory of Computation
Mar 19, 2020
1.1k
views
nielit2017dec-scientistb
theory-of-computation
context-free-grammar
1
vote
112
NIELIT 2017 DEC Scientist B - Section B: 59
A two-word instruction is stored in a location $A$. The operand part of instruction holds $B$. If the addressing mode is relative, the operand is available in location $A+B+2$ $A+B+1$ $B+1$ $A+B$
answered
in
CO and Architecture
Mar 19, 2020
1.6k
views
nielit2017dec-scientistb
co-and-architecture
addressing-modes
0
votes
113
NIELIT 2017 DEC Scientist B - Section B: 4
In a cache memory if total number of sets are ‘$s$’, then the set offset is: $2^8$ $\log_2s$ $s^2$ $s$
answered
in
CO and Architecture
Mar 19, 2020
1.6k
views
nielit2017dec-scientistb
co-and-architecture
cache-memory
0
votes
114
NIELIT 2017 DEC Scientist B - Section B: 17
The time taken to switch between user and kernel modes of execution be $t1$ while the time taken to switch between two processes be $t2$. Which of the following is TRUE? $t1>t2$ $t1=t2$ $t1<t2$ nothing can be said about the relation between $t1$ and $t2$
answered
in
Operating System
Mar 19, 2020
1.4k
views
nielit2017dec-scientistb
operating-system
context-switch
3
votes
115
NIELIT 2017 DEC Scientist B - Section B: 14
We have $10$-stage pipeline, where the branch target conditions are resolved at stage $5$. How many stalls are there for an incorrectly predicted branch? $5$ $6$ $7$ $4$
answered
in
CO and Architecture
Mar 19, 2020
1.9k
views
nielit2017dec-scientistb
co-and-architecture
pipelining
7
votes
116
NIELIT 2017 DEC Scientist B - Section B: 16
Which of the following is added to the page table in order to track whether a page of cache has been modified since it was read from the memory? Reference bit Dirty bit Tag bit Valid bit
answered
in
Operating System
Mar 19, 2020
3.2k
views
nielit2017dec-scientistb
operating-system
memory-management
paging
cache-memory
0
votes
117
NIELIT 2017 DEC Scientist B - Section B: 36
If the number of networks and number of hosts in class $B$ are $2^m, (2^n-2)$ respectively. Then the relation between $m,n$ is $3m=2n$ $7m=8n$ $8m=7n$ $2m=3n$
answered
in
Computer Networks
Mar 19, 2020
2.3k
views
nielit2017dec-scientistb
computer-networks
network-addressing
0
votes
118
NIELIT 2017 DEC Scientist B - Section B: 48
On a set $A = \{a,b,c,d\}$ a binary operation $*$ ... The relation is Commutative but not associative Neither commutative nor associative Both commutative and associative Associative but not commutative
answered
in
Set Theory & Algebra
Mar 19, 2020
1.8k
views
nielit2017dec-scientistb
discrete-mathematics
group-theory
abelian-group
0
votes
119
NIELIT 2017 DEC Scientist B - Section B: 20
Let $u$ and $v$ be two vectors in $R^2$ whose Eucledian norms satisfy $\mid u\mid=2\mid v \mid$. What is the value $\alpha$ such that $w=u+\alpha v$ bisects the angle between $u$ and $v$? $2$ $1$ $\dfrac{1}{2}$ $-2$
answered
in
Numerical Methods
Mar 19, 2020
618
views
nielit2017dec-scientistb
non-gate
vector-space
1
vote
120
NIELIT 2017 DEC Scientist B - Section B: 3
Using bisection method, one root of $x^4-x-1$ lies between $1$ and $2$. After second iteration the root may lie in interval: $(1.25,1.5)$ $(1,1.25)$ $(1,1.5)$ None of the options.
answered
in
Numerical Methods
Mar 19, 2020
2.3k
views
nielit2017dec-scientistb
non-gate
numerical-methods
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