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User topper98
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Answers by topper98
2
votes
1
NIELIT 2017 DEC Scientist B - Section B: 8
Let $A$ be an array of $31$ numbers consisting of a sequence of $0$’s followed by a sequence of $1$’s. The problem is to find the smallest index $i$ such that $A[i]$ is $1$ by probing the minimum number of locations in $A$. The worst case number of probes performed by an optimal algorithm is $2$ $4$ $3$ $5$
answered
in
Algorithms
Jun 15, 2020
1.1k
views
nielit2017dec-scientistb
algorithms
searching
array
4
votes
2
NIELIT 2017 DEC Scientist B - Section B: 5
Which of the following is machine independent optimization? Loop optimization Redundancy Elimination Folding All of the option
answered
in
Compiler Design
Jun 15, 2020
8.8k
views
nielit2017dec-scientistb
compiler-design
code-optimization
0
votes
3
GATE CSE 2008 | Question: 38
In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is: before effective address calculation has started during effective address calculation after effective address calculation has completed after data cache lookup has completed
answered
in
CO and Architecture
Jun 5, 2020
19.3k
views
gatecse-2008
co-and-architecture
virtual-memory
normal
0
votes
4
GATE CSE 2003 | Question: 10, ISRO-DEC2017-41
For a pipelined CPU with a single ALU, consider the following situations The ${j+1}^{st}$ instruction uses the result of the $j^{th}$ instruction as an operand The execution of a conditional jump instruction The $j^{th}$ and ${j+1}^{st}$ ... ALU at the same time. Which of the above can cause a hazard I and II only II and III only III only All the three
answered
in
CO and Architecture
May 26, 2020
9.5k
views
gatecse-2003
co-and-architecture
pipelining
normal
isrodec2017
1
vote
5
GATE CSE 2006 | Question: 68
Consider the relation enrolled (student, course) in which (student, course) is the primary key, and the relation paid (student, amount) where student is the primary key. Assume no null values and no foreign keys or integrity constraints. ... strictly fewer rows than Query$2$ There exist databases for which Query$4$ will encounter an integrity violation at runtime
answered
in
Databases
Apr 12, 2020
20.2k
views
gatecse-2006
databases
sql
normal
0
votes
6
GATE CSE 2016 Set 2 | Question: 30
Suppose the functions $F$ and $G$ can be computed in $5$ and $3$ nanoseconds by functional units $U_{F}$ and $U_{G}$, respectively. Given two instances of $U_{F}$ and two instances of $U_{G}$, it is required to implement ... $1 \leq i \leq 10$. Ignoring all other delays, the minimum time required to complete this computation is ____________ nanoseconds.
answered
in
CO and Architecture
Mar 24, 2020
22.7k
views
gatecse-2016-set2
co-and-architecture
data-path
normal
numerical-answers
0
votes
7
GATE CSE 2016 Set 1 | Question: 32
The stage delays in a $4$-stage pipeline are $800, 500, 400$ and $300$ picoseconds. The first stage (with delay $800$ picoseconds) is replaced with a functionality equivalent design involving two stages with respective delays $600$ and $350$ picoseconds. The throughput increase of the pipeline is ___________ percent.
answered
in
CO and Architecture
Mar 24, 2020
25.6k
views
gatecse-2016-set1
co-and-architecture
pipelining
normal
numerical-answers
0
votes
8
GATE CSE 2016 Set 1 | Question: 31
The size of the data count register of a $\text{DMA}$ controller is $16\;\text{bits}$. The processor needs to transfer a file of $29,154$ kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times ... needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is _________.
answered
in
CO and Architecture
Mar 24, 2020
18.5k
views
gatecse-2016-set1
co-and-architecture
dma
normal
numerical-answers
0
votes
9
GATE CSE 2017 Set 2 | Question: 53
Consider a machine with a byte addressable main memory of $2^{32}$ bytes divided into blocks of size $32$ bytes. Assume that a direct mapped cache having $512$ cache lines is used with this machine. The size of the tag field in bits is _______
answered
in
CO and Architecture
Mar 24, 2020
9.4k
views
gatecse-2017-set2
co-and-architecture
cache-memory
numerical-answers
8
votes
10
GATE CSE 2017 Set 1 | Question: 25
Consider a two-level cache hierarchy with $L1$ and $L2$ caches. An application incurs $1.4$ memory accesses per instruction on average. For this application, the miss rate of $L1$ cache is $0.1$; the $L2$ cache experiences, on average, $7$ misses per $1000$ instructions. The miss rate of $L2$ expressed correct to two decimal places is ________.
answered
in
CO and Architecture
Mar 24, 2020
24.2k
views
gatecse-2017-set1
co-and-architecture
cache-memory
numerical-answers
1
vote
11
GATE CSE 2018 | Question: 51
A processor has $16$ integer registers $\text{(R0, R1}, \ldots ,\text{ R15)}$ and $64$ floating point registers $\text{(F0, F1}, \ldots , \text{F63)}.$ It uses a $2\text{- byte}$ instruction format. There are four categories of ... $\text{(1F)}.$ The maximum value of $\text{N}$ is _________.
answered
in
CO and Architecture
Mar 24, 2020
24.2k
views
gatecse-2018
co-and-architecture
machine-instruction
instruction-format
numerical-answers
2-marks
0
votes
12
gate 2018 cs
physical address space of the omputer system is 2^p bytes , word size is 2^w bytes , cache memory has 2^n bytes and cache block size is 2^m words,k-way set associative is used for mapping from main memory to cache memory .the size of the tag bit is???
answered
in
CO and Architecture
Mar 24, 2020
3.5k
views
1
vote
13
GATE CSE 2018 | Question: 5
Consider the following processor design characteristics: Register-to-register arithmetic operations only Fixed-length instruction format Hardwired control unit Which of the characteristics above are used in the design of a RISC processor? I and II only II and III only I and III only I, II and III
answered
in
CO and Architecture
Mar 24, 2020
12.0k
views
gatecse-2018
co-and-architecture
cisc-risc-architecture
easy
1-mark
0
votes
14
GATE CSE 2018 | Question: 9
The following are some events that occur after a device controller issues an interrupt while process $L$ is under execution. P. The processor pushes the process status of $L$ onto the control stack Q. The processor finishes the execution of the ... based on the interrupt Which of the following is the correct order in which the events above occur? QPTRS PTRSQ TRPQS QTPRS
answered
in
Operating System
Mar 24, 2020
10.4k
views
gatecse-2018
operating-system
interrupts
normal
1-mark
2
votes
15
GATE CSE 2018 | Question: 23
A $32\text{-bit}$ wide main memory unit with a capacity of $1\;\textsf{GB}$ is built using $256\textsf{M} \times 4\text{-bit}$ DRAM chips. The number of rows of memory cells in the DRAM chip is $2^{14}$. The ... The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is _________.
answered
in
CO and Architecture
Mar 24, 2020
25.7k
views
gatecse-2018
co-and-architecture
memory-interfacing
normal
numerical-answers
1-mark
2
votes
16
GATE CSE 2019 | Question: 45
A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept ... for the memory system when the program running on the processor issues a series of read operations is ______$\times 10^6$ bytes/sec.
answered
in
CO and Architecture
Mar 24, 2020
20.3k
views
gatecse-2019
numerical-answers
co-and-architecture
cache-memory
2-marks
0
votes
17
UGC NET CSE | June 2019 | Part 2 | Question: 14
The fault can be easily diagnosed in the micro-program control unit using diagnostic tools by maintaining the contents of flags and counters registers and counters flags and registers flags, registers and counters
answered
in
CO and Architecture
Mar 24, 2020
2.5k
views
ugcnetcse-june2019-paper2
co-and-architecture
microprogram-control-unit
0
votes
18
GATE CSE 2009 | Question: 8, UGCNET-June2012-III: 58
A CPU generally handles an interrupt by executing an interrupt service routine: As soon as an interrupt is raised. By checking the interrupt register at the end of fetch cycle. By checking the interrupt register after finishing the execution of the current instruction. By checking the interrupt register at fixed time intervals.
answered
in
CO and Architecture
Mar 24, 2020
15.9k
views
gatecse-2009
co-and-architecture
interrupts
normal
ugcnetcse-june2012-paper3
0
votes
19
UGC NET CSE | June 2016 | Part 3 | Question: 5
The ____ addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are specified in the instruction. Base indexed Base indexed plus displacement Indexed Displacement
answered
in
CO and Architecture
Mar 24, 2020
3.1k
views
ugcnetcse-june2016-paper3
co-and-architecture
addressing-modes
0
votes
20
UGC NET CSE | June 2016 | Part 3 | Question: 4
The Register that stores all interrupt requests is Interrupt mask register Interrupt service register Interrupt request register Status register
answered
in
CO and Architecture
Mar 24, 2020
3.2k
views
ugcnetcse-june2016-paper3
co-and-architecture
assembly
0
votes
21
cache
In a particular system it is observed that, the cache performance get improved as a result of increasing the block size of the cache. The primary reason behing this is: 1. Program exhibits temporal locality 2. Programs have small working set 3. Read ... rather than write operation 4. Program exhibits spatial locality What would the answer to this Question ? asked in NIELIT assistant paper..
answered
in
CO and Architecture
Mar 23, 2020
1.2k
views
3
votes
22
RAM Chip
A RAM chip has 7 address line , 8 data lines and 2 chips select lines. Then the number of memory locations is ... a. 2^12 b.2^10 c.2^19 d.2^13 Plz describe with a proper diagram and significance of each lines.
answered
in
CO and Architecture
Mar 23, 2020
5.9k
views
co-and-architecture
0
votes
23
NIELIT 2017 DEC Scientist B - Section B: 47
INCA(Increase register A by $1$) is an example of which of the following addressing mode? Immediate addressing Indirect addressing Implied addressing Relative addressing
answered
in
CO and Architecture
Mar 23, 2020
2.6k
views
nielit2017dec-scientistb
co-and-architecture
addressing-modes
0
votes
24
NIELIT 2017 DEC Scientist B - Section B: 13
Consider a non-pipelined machine with $6$ stages; the lengths of each stage are $\text{20ns, 10ns, 30ns,25ns, 40 ns}$ and $\text{15ns}$ respectively. Suppose for implementing the pipelining the machine adds $\text{5 ns}$ of overhead to each stage ... What is the speed up factor of the pipelining system (ignoring any hazard impact)? $7$ $14$ $3.11$ $6.22$
answered
in
CO and Architecture
Mar 23, 2020
5.0k
views
nielit2017dec-scientistb
co-and-architecture
pipelining
0
votes
25
ISRO2015-77
In $\text{X = (M + N }\times \text{O)/(P} \times \text{Q})$, how many one-address instructions are required to evaluate it? $4$ $6$ $8$ $10$
answered
in
CO and Architecture
Mar 23, 2020
7.0k
views
memory-interfacing
co-and-architecture
machine-instruction
isro2015
1
vote
26
ISRO2015-51
How many characters per sec $(7 \;\text{bits} + 1 \;\text{parity})$ can be transmitted over a $2400$ bps line if the transfer is synchronous $( 1$ start and $1$ stop bit)? $300$ $240$ $250$ $275$
answered
in
Computer Networks
Mar 23, 2020
10.2k
views
isro2015
computer-networks
serial-communication
3
votes
27
GATE IT 2007 | Question: 44, ISRO2015-34
A hard disk system has the following parameters : Number of tracks $= 500$ Number of sectors/track $= 100$ Number of bytes /sector $= 500$ Time taken by the head to move from one track to adjacent track $= 1 \ ms$ Rotation speed $= 600 \ rpm$. What is ... time taken for transferring $250$ bytes from the disk ? $300.5 \ ms$ $255.5 \ ms$ $255 \ ms$ $300 \ ms$
answered
in
Operating System
Mar 23, 2020
22.9k
views
gateit-2007
operating-system
disk
normal
isro2015
3
votes
28
A non-pipeline system 50ns to process a task....
A non-pipeline system 50ns to process a task. The same task can be processed in a 6 segment pipeline with a clock cycle of 10ns. Determine the speed of ratio of pipeline system for 100 tasks . What is the maximum speed up that can be achieved?
answered
in
CO and Architecture
Mar 23, 2020
15.1k
views
co-and-architecture
1
vote
29
NIELIT 2016
When we move from outermost track to innermost track in a magnetic disc , density ( bits per linear inch) A. increases B.Decreases C. Remains same D. A or B Plz explain
answered
in
Unknown Category
Mar 23, 2020
2.7k
views
0
votes
30
GATE CSE 2000 | Question: 1.20, ISRO2008-47
Which of the following need not necessarily be saved on a context switch between processes? General purpose registers Translation look-aside buffer Program counter All of the above
answered
in
Operating System
Mar 23, 2020
11.9k
views
gatecse-2000
operating-system
easy
isro2008
context-switch
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