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Cache Memory
Recent questions tagged cache-memory
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151
Caching
Given the following information: TLB hit rate 95%, TLB access time is 1 cycle. cache hit rate 90 %, cache access time is 1 cycle. When TLB and cache both get miss; page fault rate is 1% The TLB access and acache access are ... cycles Access to hard drive requires 50,000 cycles. Compute the average memory access latencies when the cache is physically addresses (in cycles).
s_dr_13
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in
CO and Architecture
Mar 10, 2019
by
s_dr_13
1.1k
views
cache-memory
co-and-architecture
virtual-memory
translation-lookaside-buffer
1
vote
1
answer
152
Self-doubt
What does tag number signifies in line in cache?
Anuranjan
asked
in
CO and Architecture
Mar 9, 2019
by
Anuranjan
313
views
co-and-architecture
cache-memory
0
votes
0
answers
153
Self doubt(Hamacher and Zaky)
Memory is word addressable with 16 bit addresses Word size=16 bits Each block is of size 16 bits. The cache contains 8 blocks. What is the address division for: 1>direct. 2>associative 3>2-way set associative cache
DIYA BASU
asked
in
CO and Architecture
Feb 17, 2019
by
DIYA BASU
561
views
co-and-architecture
cache-memory
1
vote
1
answer
154
#ComputerArchitecture
If a computer executes a store, should it place the data into the cache or main memory? Cache only Main memory only Both cache and main memory Cache only OR Both cache and main memory
Reshu $ingh
asked
in
CO and Architecture
Feb 14, 2019
by
Reshu $ingh
294
views
co-and-architecture
cache-memory
23
votes
8
answers
155
GATE CSE 2019 | Question: 1
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses ... $0$ bits $28$ bits and $4$ bits $24$ bits and $4$ bits $28$ bits and $0$ bits
Arjun
asked
in
CO and Architecture
Feb 7, 2019
by
Arjun
17.8k
views
gatecse-2019
co-and-architecture
cache-memory
normal
1-mark
56
votes
11
answers
156
GATE CSE 2019 | Question: 45
A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept ... for the memory system when the program running on the processor issues a series of read operations is ______$\times 10^6$ bytes/sec.
Arjun
asked
in
CO and Architecture
Feb 7, 2019
by
Arjun
20.3k
views
gatecse-2019
numerical-answers
co-and-architecture
cache-memory
2-marks
1
vote
2
answers
157
gate 2019
Consider the cache memory size of 16kb, and cache block size is 16 bytes. The processor generates the physical address of 32 bits. Assume the cache is fully associative. What are the TAG and index bits __________ (A) 28 and 4bits (B) 28 and 0bits (C) 24 and 4bits (D) 24 and 0bits
sahil_malik
asked
in
CO and Architecture
Feb 4, 2019
by
sahil_malik
1.0k
views
co-and-architecture
cache-memory
gatecse-2019
1
vote
1
answer
158
self doubt
Main memory=512 words. block size=8 words. cache size =32 words There is an array A[100] and each element is 4 words then what is the hit ratio for the following loop. for(i=0;i<=9;i++) { for(j=0;j<=9;j=j+2) { A[i][j]=A[i][j]+20; } }
DIYA BASU
asked
in
CO and Architecture
Feb 3, 2019
by
DIYA BASU
318
views
co-and-architecture
cache-memory
array
0
votes
1
answer
159
self doubt
Main memory=512 words. block size=8 words. cache size =32 words what is tag,line no.,block offset bits
DIYA BASU
asked
in
CO and Architecture
Feb 3, 2019
by
DIYA BASU
364
views
co-and-architecture
cache-memory
0
votes
0
answers
160
self doubt
https://gateoverflow.in/2308/gate1993-11 This question can also be solved as a probability question where the random space contains (M1),(M1,M2),(M1,M2,M3) and let X be the random variable which gives the time for any of the three options selected from the ... space and correspondingly we give the PMF for each time selected and then we find the expectation?? Am I correct with my logic??
DIYA BASU
asked
in
CO and Architecture
Feb 2, 2019
by
DIYA BASU
199
views
co-and-architecture
cache-memory
self-doubt
0
votes
1
answer
161
SELF DOUBT
If main memory size=128KB. cache size 16KB . block size 256B. And memory is word addressable each word is 4B . Then is the address divided into : tag=3bits. line no=6 bits block offset=6 bits???(PLEASE VERIFY) We use DIRECT MAPPING.
DIYA BASU
asked
in
CO and Architecture
Feb 2, 2019
by
DIYA BASU
316
views
co-and-architecture
cache-memory
3
votes
1
answer
162
ME adv mock
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size ... words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is_____ (Upto 2 decimal places)
newdreamz a1-z0
asked
in
CO and Architecture
Feb 1, 2019
by
newdreamz a1-z0
847
views
co-and-architecture
cache-memory
0
votes
1
answer
163
GRADEUP
For a 4 bit set associative cache 10 bits are required as index to specify cache block. The main memory is of size 4G x 32. Size of cache memory is? Answer is 4096*49. Please explain the notation also.
Aman Janko
asked
in
CO and Architecture
Feb 1, 2019
by
Aman Janko
500
views
co-and-architecture
cache-memory
1
vote
2
answers
164
made easy test series
please provide a detailed solution
Vignaneswarkrishna
asked
in
CO and Architecture
Feb 1, 2019
by
Vignaneswarkrishna
595
views
co-and-architecture
cache-memory
1
vote
0
answers
165
Cache
Please tell what happens to hit rate, hit time, compulsory miss rate, conflict miss rate, capacity miss rate, miss time on : 1. Increasing Cache size 2. Increasing Block size 3. Increasing number of lines 4. Increasing Associativity
Balaji Jegan
asked
in
CO and Architecture
Jan 31, 2019
by
Balaji Jegan
540
views
co-and-architecture
cache-memory
0
votes
0
answers
166
Cache acess
I know the acess time to a sequential acess cache is given as Hitrate*(Cache acess time)+ Miss rate*(Cachec acess time + Mem acess time) Now in question if they explicitly say in case of miss data is obtained from memory and put into cache and again ... , will my formula change Hirate(Cache acess time)+ Misseate* ( Cache acess time+ Mem acess time + Cache acess time) pls help me
Aravind Adithya 1
asked
in
CO and Architecture
Jan 31, 2019
by
Aravind Adithya 1
337
views
co-and-architecture
cache-memory
4
votes
1
answer
167
MadeEasy Test Series 2019: CO & Architecture- Cache Memory
Consider a n-way cache with 'x blocks of 64 words each. The main memory of the system is having 8 million words. Size of the tag field is 16 bits and additional memory required for tags is 1024 bytes. What will be the values of n and x respectively? Answer 256 512
Ram Swaroop
asked
in
CO and Architecture
Jan 30, 2019
by
Ram Swaroop
1.5k
views
co-and-architecture
cache-memory
made-easy-test-series
5
votes
1
answer
168
MadeEasy Test Series 2019: CO & Architecture - Cache Memory
A CPU cache is organized into 2 level cache L1 and L2 The penalty for L1 cache miss and L2 cache miss are 60 and 30 respectively for 1200 memory references The hit time of L1 and L2 are 5 and 10 clock cycles and penalty for L2 cache miss to main memory is 70 clock cycles. The average memory access time will be
Ram Swaroop
asked
in
CO and Architecture
Jan 29, 2019
by
Ram Swaroop
1.2k
views
co-and-architecture
cache-memory
made-easy-test-series
0
votes
1
answer
169
MadeEasy Full Length Test 2019: CO & Architecture - Cache Memory
Consider a 2 way set associative cache with 4 blocks. The memory block requests in the order. 4,6,3,8,5,6,0,15,6,17,20,15,0,8 If LRU is used for block replacement then memory set 17 will be in the cache block ____. (PS: the given answer is 1)
snaily16
asked
in
CO and Architecture
Jan 28, 2019
by
snaily16
788
views
co-and-architecture
cache-memory
made-easy-test-series
0
votes
0
answers
170
Computer organisation cache
Why can't we have n-levels of cache ?
Priyansh Singh
asked
in
CO and Architecture
Jan 27, 2019
by
Priyansh Singh
602
views
cache-memory
co-and-architecture
multilevel-cache
0
votes
1
answer
171
ME Test series question
A computer uses two level cache L1 and L2 and in 2000 memory references there are 320 misses in L1 cache and 150 misses in L2lcache. If the miss penalty of L2 is 300 clock cycles, hit time of L1 is 1 clock cycle and hit time of L2 is 10 clock cycles what is the average memory access time?
Shankar Kakde
asked
in
CO and Architecture
Jan 25, 2019
by
Shankar Kakde
353
views
co-and-architecture
cache-memory
0
votes
1
answer
172
Cache Organization
Can any one help me out with this question : This was asked in MadeEasy CBT held on 23rd jan
Nandkishor3939
asked
in
CO and Architecture
Jan 25, 2019
by
Nandkishor3939
1.0k
views
cache-memory
co-and-architecture
effective-memory-access
0
votes
1
answer
173
MadeEasy Full Length Test 2019: CO & Architecture - Cache Memory
All is fine but how did they calculate the miss rate of level 2 cache (L2) i.e.how is m2=0.46875?
Iamniks4
asked
in
CO and Architecture
Jan 24, 2019
by
Iamniks4
670
views
cache-memory
co-and-architecture
made-easy-test-series
1
vote
1
answer
174
Ace Test Series: CO & Architecture - Cache Memory
Na462
asked
in
CO and Architecture
Jan 21, 2019
by
Na462
739
views
co-and-architecture
cache-memory
ace-test-series
associative-memory
1
vote
0
answers
175
Ace Test Series: CO & Architecture - Cache Misses Type
Na462
asked
in
CO and Architecture
Jan 21, 2019
by
Na462
919
views
cache-memory
co-and-architecture
misses
ace-test-series
0
votes
0
answers
176
ME TEST
A byte addressable computer has a small data cache capable of holding 16 32-bit words. Each cache block consist of four 32 bits words. For the following sequence of main memory addresses (in hexadecimal). The conflict miss if 2-way set associative LRU cache is used is_____ 100,108, 114 ... what will be the address partition look like. 1. tag(7) set(1) offset(4) 2. tag(7) set(1) offset(2)
newdreamz a1-z0
asked
in
CO and Architecture
Jan 21, 2019
by
newdreamz a1-z0
377
views
co-and-architecture
cache-memory
least-recently-used
0
votes
0
answers
177
find conflict misses
here it is given byte addressable. So these locations refer to words or byte location. What are set, block fields here : number of words or number of bytes for these location.
bts1jimin
asked
in
CO and Architecture
Jan 17, 2019
by
bts1jimin
454
views
co-and-architecture
misses
cache-memory
0
votes
0
answers
178
ME-MT-CO+OS
consider a 2-level $L_1$ and $L_2$ memory hierarchy system.The associativity of $L_1$ towards processor is more .$L_1$(cache ) has accessing time of 15 ns and $L_2$ (main memory) has an accessing time of 100 ns .writing takes 30 ns for $L_1$ and 150 ns for $L_2$.assume ... simultaneously so $T_w=150 ns$ $T_r=.7*15ns+.3*(100ns+15ns)=45ns$ $T_{avg}=.5*45+.5*150=97.5ns$ please verify it.
Prateek Raghuvanshi
asked
in
CO and Architecture
Jan 17, 2019
by
Prateek Raghuvanshi
316
views
co-and-architecture
cache-memory
1
vote
1
answer
179
Applied Course | Mock GATE | Test 1 | Question: 54
The common pattern in code for using cache systems looks like the following. In this example get_from_cache() returns zero when the data was not in the cache. int lookup(int key) { int data; data = get_from_cache(key); if (data == 0) { data = get_from_backing_store( ... $1 \: ms$ $6 \: ms$ $30 \: ms$ $95 \: ms$
Applied Course
asked
in
CO and Architecture
Jan 16, 2019
by
Applied Course
428
views
applied-course-2019-mock1
co-and-architecture
cache-memory
0
votes
1
answer
180
Computer system organization cache memory
Assume that A, B , and C are memory addresses each of which are in different block of memory. Further assume A, B , C are generated in a uniformly random way. What is the probability that the second instance of "B" will be a hit on a 4-line direct-mapped cache?
Nikita Shadija
asked
in
CO and Architecture
Jan 16, 2019
by
Nikita Shadija
387
views
co-and-architecture
cache-memory
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