Dark Mode

Recent questions tagged cache-memory

0 votes

0 answers

181

textbook
consider a 12 bit physical address and a direct-mapped cache with 64 blocks and each block has a size of 16 bytes. To which block number does the byte address 1200 map?

suneetha asked in CO and Architecture Jan 14, 2019

720 views

1 vote

0 answers

182

Applied Course
Consider a computer system in which cache memory write hit takes 5ns and and miss takes 80ns. Cache memory read hit takes 2ns and miss takes 40ns. The cache is having 95% hit. The system received 1000 instructions out of which, 700 operand fetch operations and 300 operand write operations. The average time taken ... 2+ (1-h1)*40 = 2 + (0.05)*4 OR h1*2+ (1-h1)*40 =0.95*2+(0.05)*40 ?

dharmesh7 asked in CO and Architecture Jan 14, 2019

857 views

0 votes

0 answers

183

applied-course-mock-3
Consider a computer system in which cache memory write hit takes 5ns and and miss takes 80ns. Cache memory read hit takes 2ns and miss takes 40ns. The cache is having 95% hit. The system received 1000 instructions out of which, 700 operand fetch operations and 300 operand write operations. The average time taken to execute above 1000 instructions is___________?

Prateek Raghuvanshi asked in CO and Architecture Jan 14, 2019

by Prateek Raghuvanshi

644 views

0 votes

1 answer

184

MadeEasy CBT Test 2019: CO & Architecture - Cache Memory
consider a computer with 4 GB main memory synchronized with CPU speed using 8-way set associative cache of 16 KB. memory system is organized into 64 word blocks and word length of CPU is 64 bits. the size of tag in cache line in the set is ______ bits. (answer is 21)

Satbir asked in CO and Architecture Jan 14, 2019

by Satbir

693 views

0 votes

0 answers

185

Computer Architec
True or False! Tag field is ratio of Main memory to cache memory. i.e MM size =2^m unit and Cache size =2^n unit the tag field will be of (m-n) size.

Abhisek Tiwari 4 asked in CO and Architecture Jan 14, 2019

by Abhisek Tiwari 4

219 views

0 votes

2 answers

186

Ace Test Series 2019: CO & Architecture - Cache Memory Tag Size

Shankar Kakde asked in CO and Architecture Jan 13, 2019

by Shankar Kakde

488 views

1 vote

3 answers

187

MadeEasy Subject Test: CO & Architecture - Cache Memory
A cache memory is 30 times faster than main memory (MM) and 50% of the time cache is referred for the execution of instruction. The performance is gained by introducing this cache is ________. What I did EMAT = 0.5(M/30)+0.5(M/30+M) = 32M/60 speed up= (M)/32M/60) =60/32=1.875 answer given is 1.90-1.97 (using amdhal’s law)

Shivam Kasat asked in CO and Architecture Jan 13, 2019

by Shivam Kasat

919 views

0 votes

1 answer

188

Effective Access Time
A Computer uses two level Cache L1 and L2 and in 2000 memory references there are 320 misses in L1 and 150 misses in L2. If Miss penalty of L2 is 300 clock cycles, hit time of L1 is 1 clock cycle and hit time in L2 is 10 clock cycle .What is average memory access time ? 3.6 cycles 5.4 cycles 25.06 cycles 4.8 cycles

Na462 asked in CO and Architecture Jan 12, 2019

by Na462

879 views

0 votes

1 answer

189

Self doubt about LRU and Direct mapping cache
Can we apply LRU policy to direct mapped cache. according to me it doesn't make any sense as eventually it will be like FIFO only as unique memory addresses are assigned to each cache line. But my doubt / confusion is can we implement LRU on direct mapped caches?

S Ram asked in CO and Architecture Jan 12, 2019

by S Ram

493 views

0 votes

0 answers

190

VIRTUAL GATE TEST SERIES

Ajay Maurya 6 asked in CO and Architecture Jan 10, 2019

by Ajay Maurya 6

284 views

1 vote

1 answer

191

MadeEasy Test Series: CO & Architecture - Cache Memory

Shubham Kumar Gupta asked in CO and Architecture Jan 10, 2019

by Shubham Kumar Gupta

617 views

2 votes

1 answer

192

MadeEasy Test Series: CO & Architecture - Cache Memory
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to ... up of processor is achieved in dealing with average read miss after increasing the line size is (Upto 2 decimal places)

Jay Bhutada 1 asked in CO and Architecture Jan 9, 2019

by Jay Bhutada 1

690 views

0 votes

0 answers

193

GATE 2019 2-way set associative
plz explain …..??

Vikas123 asked in Operating System Jan 7, 2019

355 views

1 vote

1 answer

194

MadeEasy Test Series: CO & Architecture - Cache Memory
A CPU has recorded 450 memory references. The CPU has been organized into 2-level of cache memory L1 and L2 . There are 50 misses and 25 misses in L1 and L2 respectively. The miss penalty from L2 cache to memory is 60 cycles and hit time of L2 cache is 30 cycles. What is the average stall (in cycles) per instruction.? 20 40 80 32

Shivam Kasat asked in CO and Architecture Jan 7, 2019

by Shivam Kasat

800 views

0 votes

2 answers

195

MadeEasy Test Series: CO & Architecture - Cache Memory

jatin khachane 1 asked in CO and Architecture Jan 7, 2019

by jatin khachane 1

551 views

0 votes

0 answers

196

Access time
What is formula of Average memory access time? And formula of effective access time? And the difference between them . I always mix them .

Alina asked in CO and Architecture Jan 6, 2019

by Alina

386 views

0 votes

0 answers

197

UPPCL AE 2018:67
Consider a fully-associative data cache with $32$ blocks of $64$ bytes each. The cache uses $\text{LRU}$ (Least Recently Used) replacement. Consider the following $\text{C}$ code to sum together all of the elements of a $64$ by $64$ two-dimensional array ... all blocks in the cache are initially invalid. How many cache misses will result from the code? $256$ $128$ $1024$ $512$

admin asked in CO and Architecture Jan 5, 2019

by admin

313 views

0 votes

0 answers

198

UPPCL AE 2018:32
Which of the following statement is $\text{TRUE}$? Doubling the block size and halving the number of sets will reduce capacity misses The last-level cache is designed for high capacity rather than low latency Workloads with high temporal locality benefit from smaller cache block sizes Workloads with high spatial locality benefit from smaller cache block sizes

admin asked in CO and Architecture Jan 5, 2019

by admin

191 views

0 votes

1 answer

199

UPPCL AE 2018:21
Assume a memory access to main memory on a cache “miss” takes $30 \; \text{ns}$ and a memory access to the cache (on a cache “hit”) takes $3 \; \text{ns}.$ If $80 \%$ of the processor’s memory requests result in a cache “hit”, what is the average memory access time? $8.4 \text{ns}$ $9 \text{ns}$ $4.4 \text{ns}$ $2.2 \text{ns}$

admin asked in Operating System Jan 5, 2019

by admin

565 views

0 votes

0 answers

200

Self Doubt
What does additional memory for tags refer to in Direct Mapping, Associative Mapping and Set- Associative Mapping?

manisha11 asked in CO and Architecture Jan 5, 2019

217 views

0 votes

1 answer

201

UPPCL 2018AE
Suppose when there is cache “Miss” then memory Access is 30ns and when cache “Hit” then memory access time is 3ns if 80% is cache hit then effective memory access 9ns 8.4ns 3ns 9.10ns

pream sagar asked in CO and Architecture Dec 31, 2018

1.3k views

0 votes

0 answers

202

Success Gateway , cache-misses 2D array
When the first element is fetched , some elements/values not in the array will be fetched as it is not starting from block offset 0 ,and the memory is having capacity to exactly hold all array elements , so i think there will be ... apart from 64 which are necessary. Can someone please tell me where I'm wrong or some better approach for these questions?

Anuj Mishra asked in CO and Architecture Dec 30, 2018

277 views

0 votes

0 answers

203

#Madeeasy
A 4way set associative cache lines of 32 bytes and a cache size of 16kb. Which of the below main memory blocks is mapped to set 13 of the cache memory when 16mb main memory is used? (A295D0,FCED9D,2FA0D0,F0A1B5)

BHOJARAM asked in CO and Architecture Dec 30, 2018

311 views

10 votes

3 answers

204

Gateoverflow Computer architecture 2 exam question
Suppose there are 500 memory references in which 50 misses in the 1st level cache and 20 misses in the 2nd level cache . Let the miss penalty from L2 cache to memory is 100 cycles . Hit time in L2 cache is 20 cycles and hit ... per instruction will be __________ Ans is : 15 Can any explain how to solve this type of question, Thanks in advance.

hitendragarg001 asked in CO and Architecture Dec 30, 2018

by hitendragarg001

1.4k views

0 votes

0 answers

205

ME-FT
assume a CPU processor is designed with FIFO replacement policy and memory is byte addressable .processor uses cache memory for faster output. A set of instruction is executed on the the processor and hit / miss outcome is shown below in table: memory reference outcome 0 miss 16 miss ... 23 miss 3 hit which of the following is the possible associativity and block size in byte? 2,4 2,8 4,2 2,2

Prateek Raghuvanshi asked in CO and Architecture Dec 29, 2018

by Prateek Raghuvanshi

537 views

0 votes

1 answer

206

MADEEASY- CO - SET Associative mapping
Assume a new cache design is proposed by a student. But he later discovered design has too many conflict misses and to resolve this issue he increases the associativity in the design. Which of the following implication will occur in the ... bit increases C. No implications in the design what does INDEX bits refers to in set associative and associative mapping?

Markzuck asked in CO and Architecture Dec 29, 2018

788 views

2 votes

0 answers

207

MadeEasy Test Series: CO & Architecture - Cache Memory
Consider the following statements: S1: Direct mapped caches do not need a cache block replacement policy, where as fully associative cache need. S2:: Direct mapped cache, may produce more misses if programs refers to memory words that occupy a same tag value. Which of the following options is correct? How S1 is true?

Shivam Kasat asked in CO and Architecture Dec 28, 2018

by Shivam Kasat

1.9k views

0 votes

0 answers

208

#Cache #EffectiveAddressTime
While calculating Effective Address Time, Should we consider sequential access or parallel access by default?

Amit625 asked in CO and Architecture Dec 28, 2018

427 views

13 votes

1 answer

209

GATE Overflow | Mock GATE | Test 1 | Question: 41
Consider a Computer system with a single core CPU, a single level of cache of size $4 \text{MB}$, and main memory. It takes one CPU cycle to access a memory byte if it is in cache, and $145$ cycles if the memory access incurs a cache miss and must be fetched ... $B$ is read in sequence as follows: for (i=0;i<N;i++) { read A[i]; read B{i]; }

Ruturaj Mohanty asked in CO and Architecture Dec 27, 2018

by Ruturaj Mohanty

1.5k views

5 votes

1 answer

210

GATE Overflow | Mock GATE | Test 1 | Question: 64
Consider the $2$ dimensional array $A$: int A[][]=new int[100][100]; where $A[0][0]$ is at location $800$ in a paged memory system with pages of size $800 bytes$. Each int type needs 4 bytes and A is stored in row-major order. A small process that ... other $2$ are initially empty? for (int i=0;i<100;i++) for (int j=0;j<100; j++) A[j][i]=1;

Ruturaj Mohanty asked in Operating System Dec 27, 2018

by Ruturaj Mohanty

1.2k views

Page:

« prev
1
2
3
4
5
6
7
8
9
10
11
12
...
25
next »

Recent questions tagged cache-memory