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2
votes
31
Morris Mano Edition 3 Exercise 5 Question 6 (Page No. 198)
Assume that the EXCLUSIVE-OR gate has a propagation delay of 20ns and that the AND and OR gates have a Propagation delay of 10ns. What is the total Propagation delay time in the four-bit adder of the figure given below?
answered
in
Digital Logic
Aug 31, 2020
5.4k
views
digital-logic
morris-mano
combinational-circuit
adder
0
votes
32
Full adder
answered
in
Digital Logic
Aug 31, 2020
961
views
digital-logic
carry-generator
adder
full-adder
0
votes
33
MadeEasy Test Series: Digital Logic - Adder
A 1-bit full adder circuit takes 5 ns to generate the carry-out bit and 10 ns for the sum-bit. When 4, 1-bit full adders are cascaded, the maximum rate of additions per second will be _______ × 107.
answered
in
Digital Logic
Aug 31, 2020
1.4k
views
made-easy-test-series
digital-logic
adder
1
vote
34
GATE IT 2004 | Question: 43
The number $(123456)_8$ is equivalent to $\text{(A72E)}_{16}$ and $(22130232)_4$ $\text{(A72E)}_{16}$ and $(22131122)_4$ $\text{(A73E)}_{16}$ and $(22130232)_4$ $\text{(A62E)}_{16}$ and $(22120232)_4$
answered
in
Digital Logic
Aug 29, 2020
4.3k
views
gateit-2004
digital-logic
number-representation
normal
7
votes
35
GATE CSE 2000 | Question: 2.14
Consider the values of $A = 2.0 \times 10^{30}, B = -2.0 \times 10^{30}, C = 1.0,$ and the sequence X:= A + B Y:= A + C X:= X + C Y:= Y + B executed on a computer where floating point numbers are represented with $32$ bits. The values for $X$ and $Y$ will be $X = 1.0, Y = 1.0$ $X = 1.0, Y = 0.0$ $X = 0.0, Y = 1.0$ $X = 0.0, Y = 0.0$
answered
in
Digital Logic
Aug 29, 2020
12.0k
views
gatecse-2000
digital-logic
number-representation
normal
0
votes
36
ISRO-DEC2017-71
A $32$-$bit$ adder is formed by cascading $4$-$bit$ CLA adder.The gate delays (latency) for getting the sum bits is $16$ $18$ $17$ $19$
answered
in
Digital Logic
Aug 27, 2020
6.9k
views
isrodec2017
2
votes
37
GATE CSE 1999 | Question: 2.16
The number of full and half-adders required to add $16$-bit numbers is $8$ half-adders, $8$ full-adders $1$ half-adder, $15$ full-adders $16$ half-adders, $0$ full-adders $4$ half-adders, $12$ full-adders
answered
in
Digital Logic
Aug 27, 2020
22.3k
views
gate1999
digital-logic
normal
adder
0
votes
38
GATE CSE 2016 Set 1 | Question: 33
Consider a carry look ahead adder for adding two $n$-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is $\Theta (1)$ $\Theta (\log(n))$ $\Theta (\sqrt{n})$ $\Theta (n)$)
answered
in
Digital Logic
Aug 27, 2020
31.0k
views
gatecse-2016-set1
digital-logic
adder
normal
1
vote
39
GATE CSE 2004 | Question: 62
A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time ... the carry network has been implemented using two-level AND-OR logic. 4 time units 6 time units 10 time units 12 time units
answered
in
Digital Logic
Aug 27, 2020
32.4k
views
gatecse-2004
digital-logic
normal
adder
0
votes
40
GATE CSE 2014 Set 3 | Question: 8
Consider the following combinational function block involving four Boolean variables $x,\:y,\:a,\:b$ where $x,\:a,\:b$ are inputs and $y$ is the output. f(x, a, b, y) { if(x is 1) y = a; else y = b; } Which one of the following digital logic blocks is the most suitable for implementing this function? Full adder Priority encoder Multiplexor Flip-flop
answered
in
Digital Logic
Aug 27, 2020
7.1k
views
gatecse-2014-set3
digital-logic
easy
digital-circuits
0
votes
41
GATE CSE 2007 | Question: 34
Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of $n$ variables. What is the minimum size of the multiplexer needed? $2^n$ line to $1$ line $2^{n+1}$ line to $1$line $2^{n-1}$ line to $1$line $2^{n-2}$ line to $1$line
answered
in
Digital Logic
Aug 27, 2020
31.5k
views
gatecse-2007
digital-logic
normal
multiplexer
4
votes
42
GATE CSE 2013 | Question: 5
In the following truth table, $V = 1$ ... What function does the truth table represent? Priority encoder Decoder Multiplexer Demultiplexer
answered
in
Digital Logic
Aug 27, 2020
8.2k
views
gatecse-2013
digital-logic
normal
digital-circuits
3
votes
43
ISRO2018-9
In the diagram above, the inverter (NOT gate) and the AND-gates labeled $1$ and $2$ have delays of $9, 10$ and $12$ nanoseconds (ns), respectively. Wire delays are negligible. For certain values $a$ and $c$, together with certain transition of $b$, a glitch (spurious output) is ... correct value. The duration of glitch is: $7\;\text{ns}$ $9\;\text{ns}$ $11\;\text{ns}$ $13\;\text{ns}$
answered
in
Digital Logic
Aug 25, 2020
6.0k
views
isro2018
digital-logic
circuit-output
0
votes
44
the boolean expression y=(a+b'+a'b)c' is given by
answered
in
Digital Logic
Aug 25, 2020
7.8k
views
boolean-algebra
0
votes
45
UGC NET CSE | Junet 2015 | Part 3 | Question: 15
The process of dividing an analog signal into a string of discrete outputs, each of constant amplitude, is called: Strobing Amplification Conditioning Quantization
answered
in
Computer Networks
Aug 25, 2020
1.5k
views
ugcnetcse-june2015-paper3
analog-&-digital-transmission
computer-networks
0
votes
46
UGC NET CSE | June 2016 | Part 2 | Question: 6
Which of the following logic expression is incorrect ? $1 \oplus 0 =1$ $1 \oplus 1 \oplus 1=1$ $1 \oplus 1 \oplus 0=1$ $1 \oplus 1 =0$
answered
in
Digital Logic
Aug 25, 2020
4.3k
views
ugcnetcse-june2016-paper2
digital-logic
2
votes
47
ISRO2014-56
Which of the following is not valid Boolean algebra rule? $\text{X.X = X}$ $\text{(X+Y).X = X}$ $\overline{X}+\text{XY = Y}$ $\text{(X+Y).(X+Z) = X + YZ}$
answered
in
Digital Logic
Aug 25, 2020
4.1k
views
digital-logic
boolean-algebra
isro2014
2
votes
48
ISRO2014-53
Consider the logic circuit given below. The inverter, AND and OR gates have delays of $6, 10$ and $11$ nanoseconds respectively. Assuming that wire delays are negligible, what is the duration of glitch for $\text{Q}$ before it becomes stable? $5$ $11$ $16$ $27$
answered
in
Digital Logic
Aug 25, 2020
5.3k
views
isro2014
digital-logic
circuit-output
0
votes
49
#Digital logic
The output of a tristate buffer when the enable input in 0 is Always 0 Always 1 Retains the last value when enable input is high Disconnected state
answered
in
Digital Logic
Aug 25, 2020
222
views
0
votes
50
GATE CSE 2016 Set 2 | Question: 08
Let, $x_{1} ⊕ x_{2} ⊕ x_{3} ⊕ x_{4}= 0$ where $x_{1}, x_{2}, x_{3}, x_{4}$ are Boolean variables, and $⊕$ is the XOR operator. Which one of the following must always be TRUE? $x_{1}x_{2}x_{3}x_{4} = 0$ $x_{1}x_{3} + x_{2} = 0$ $\bar{x}_{1} ⊕ \bar{x}_{3} = \bar{x}_{2} ⊕ \bar{x}_{4}$ $x_{1} + x_{2} + x_{3} + x_{4} = 0$
answered
in
Digital Logic
Aug 24, 2020
13.5k
views
gatecse-2016-set2
digital-logic
boolean-algebra
normal
0
votes
51
GATE CSE 2015 Set 2 | Question: 37
The number of min-terms after minimizing the following Boolean expression is _______. $[D'+AB'+A'C+AC'D+A'C'D]'$
answered
in
Digital Logic
Aug 24, 2020
18.7k
views
gatecse-2015-set2
digital-logic
boolean-algebra
normal
numerical-answers
1
vote
52
GATE CSE 2008 | Question: 8
Given $f_1$, $f_3$ and $f$ in canonical sum of products form (in decimal) for the circuit $f_1 = \Sigma m(4, 5, 6, 7, 8)$ $f_3 = \Sigma m(1, 6, 15)$ $f = \Sigma m(1, 6, 8, 15)$ then $f_2$ is $\Sigma m(4, 6)$ $\Sigma m(4, 8)$ $\Sigma m(6, 8)$ $\Sigma m(4, 6, 8)$
answered
in
Digital Logic
Aug 24, 2020
9.4k
views
gatecse-2008
digital-logic
canonical-normal-form
easy
1
vote
53
GATE CSE 2013 | Question: 21
Which one of the following expressions does NOT represent exclusive NOR of $x$ and $y$? $xy + x′ y′$ $x\oplus y′$ $x′\oplus y$ $x′\oplus y′$
answered
in
Digital Logic
Aug 24, 2020
9.4k
views
gatecse-2013
digital-logic
easy
boolean-algebra
0
votes
54
GATE CS Mock 2018
Suppose there are two singly linked lists both of which intersect at some point and become a single linked list. The head or start pointers of both the lists are known, but the intersecting node and lengths of lists are not known. What is worst case time complexity of optimal ... n), where m, n are lengths of given lists D) Θ(min(n, m)), where m, n are lengths of given lists
answered
in
DS
Aug 22, 2020
4.0k
views
usergate2018
usermod
0
votes
55
GATE CSE 2002 | Question: 2.19
To evaluate an expression without any embedded function calls One stack is enough Two stacks are needed As many stacks as the height of the expression tree are needed A Turing machine is needed in the general case
answered
in
Compiler Design
Aug 21, 2020
9.9k
views
gatecse-2002
compiler-design
expression-evaluation
easy
0
votes
56
UGC NET CSE | December 2014 | Part 2 | Question: 24
Consider an array $A\left[20, 10\right]$, assume $4$ words per memory cell and the base address of array $A$ is $100$. What is the address of $A\left[11, 5\right]$ ? Assume row major storage. $560$ $565$ $570$ $575$
answered
in
Programming in C
Aug 21, 2020
19.5k
views
ugcnetcse-dec2014-paper2
array
row-major-address-calculation
0
votes
57
UGC NET CSE | December 2015 | Part 2 | Question: 16
A three dimensional array in 'C' is declared as int A[x][y][z]. Here, the address of an item at the location A[p][q][r] can be computed as follows: (where w is the word length of an integer) &A[0][0][0]+w(y*z*q+z*p+r) &A[0][0][0]+w(y*z*p+z*q+r) &A[0][0][0]+w(x*y*p+z*q+r) &A[0][0][0]+w(x*y*q+z*p+r)
answered
in
Programming and DS
Aug 21, 2020
5.2k
views
ugcnetcse-dec2015-paper2
programming-in-c
three-dimensional-array
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